On-chip self calibrating delay monitoring circuitry

Abstract

The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

1. A circuit arrangement comprising:
 a launching flip-flop configured to output a state transition from a first state to a second, different state based upon a state transition at an input thereof; 
 a programmable delay line coupled to the launching flip-flop, the programmable delay line comprising a configuration unit, wherein the programmable delay line is configured to propagate the state transition from the launching flip-flop therethrough, and wherein a time to propagate the state transition therethrough is associated with a delay time of the programmable delay line; 
 a time-to-digital converter coupled to the programmable delay line, the time-to-digital converter comprising at least one delay element coupled to a respective sampling flip-flop, wherein the time-to-digital converter is configured to measure the delay time of the programmable delay line; and 
 a feedback loop circuit coupled to the time-to-digital converter and to the configuration unit, wherein the feedback loop circuit is adapted to compare the measured delay time to a predetermined target value and provide at least one input signal to the configuration unit based on a result of the comparison. 
 
     
     
       2. The circuit arrangement of  claim 1 , wherein the feedback loop circuit comprises an evaluation circuit to receive the at least one output signal from the time-to-digital converter and to provide the at least one input signal to the configuration unit. 
     
     
       3. The circuit arrangement of  claim 1 , wherein the feedback loop circuit is adapted to provide the at least one input signal to the configuration unit during a calibration mode. 
     
     
       4. The circuit arrangement of  claim 1 , wherein the configuration unit comprises an arithmetic logic unit and a configuration register, the arithmetic logic unit coupled to the feedback loop and coupled to the configuration register, the configuration register is adapted to store at least one configuration setting of the programmable delay line, and the arithmetic logic unit is adapted to provide at least one signal to the configuration register to change the at least one configuration setting of the programmable delay line based on the at least one input signal received from the feedback loop. 
     
     
       5. The circuit arrangement of  claim 1 , wherein the feedback loop, the configuration unit, and the programmable delay line are configured to provide a digital-to-time converter. 
     
     
       6. The circuit arrangement of  claim 1 , wherein the feedback loop circuit is not adapted to provide the at least one input signal to the configuration unit during a measurement mode. 
     
     
       7. The circuit arrangement of  claim 1 , wherein the launching flip-flop, the programmable delay line, the time to digital converter, and the feedback loop circuit are integrated on the same integrated circuit, and wherein a calibration mode is activated when processes executed by the integrated circuit change from a first type of process to a second type of process, when the integrated circuit is configured to execute processes of more than one type, or a combination thereof. 
     
     
       8. The circuit arrangement of  claim 7 , wherein the integrated circuit is configured to execute the first type of process and the second type of process utilizing a different supply voltage, a different clock frequency, or a combination thereof. 
     
     
       9. The circuit arrangement of  claim 1 , wherein the feedback loop circuit is further configured to compare the measured delay time to a predetermined threshold value that is different from the predetermined target value in a measurement mode, and provide an output signal indicating a possible timing violation if the measured delay time exceeds the predetermined threshold value. 
     
     
       10. The circuit arrangement of  claim 9 , wherein the feedback loop circuit is further configured to provide a different output signal indicating a slack margin if the measured delay time is less than the predetermined threshold value, wherein the slack margin reflects a magnitude of a difference between the measured delay time and the predetermined threshold value.