Processing clock signals

Abstract

A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.

1. A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit comprising:
 an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; 
 a first pass gate for receiving the inverted first clock edge and outputting a first trigger signal of a first polarity; and 
 a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; 
 whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal. 
 
     
     
       2. A circuit according to  claim 1 , wherein each of the first and second pass gates comprise a complementary pair of transistors connected in parallel. 
     
     
       3. A circuit according to  claim 1 , wherein a PMOS transistor of the first pass gate is supplied with a first voltage level at its gate terminal that opens the PMOS transistor, and an NMOS transistor of the first pass gate is supplied with a second voltage level at its gate terminal that opens the NMOS transistor. 
     
     
       4. A circuit according to  claim 1 , wherein a PMOS transistor of the second pass gate is supplied at its gate terminal with the output of said inverter and an NMOS transistor of the second pass gate is supplied with the second voltage level at its gate terminal that opens the NMOS transistor. 
     
     
       5. A circuit according to  claim 1 , wherein a NMOS transistor of the second pass gate is supplied at its gate terminal with the output of said inverter and a PMOS transistor of the second pass gate is supplied with the first signal at its gate terminal that turns the PMOS transistor on. 
     
     
       6. A circuit according to  claim 3 , wherein the first and second trigger signals are rising edges if the second clock edge is a rising edge. 
     
     
       7. A circuit according to  claim 1 , wherein the circuit further comprises buffer circuitry configured to supply the clock edges to said inverter. 
     
     
       8. A circuit according to  claim 1 , wherein the circuit further comprises buffer circuitry configured to receive the first trigger signal and buffer circuitry configured to receive the second trigger signal. 
     
     
       9. A circuit according to  claim 7 , wherein the buffer circuitry comprises an even number of inverters. 
     
     
       10. A circuit according to  claim 8 , wherein the buffer circuitry comprises an even number of inverters. 
     
     
       11. A circuit according to  claim 1 , wherein said delay is in the order of picoseconds. 
     
     
       12. A method of processing a clock signal including first and second clock edges of different polarities, the method comprising:
 inverting a first clock edge to generate an inverted first clock edge and passing the inverted clock edge through a first pass gate to output a first trigger signal of a first polarity; 
 inverting a second clock edge to generate an inverted second clock edge; and 
 supplying the second clock edge to a second pass gate to output a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; 
 whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and the second trigger signal. 
 
     
     
       13. A method according to  claim 12 , wherein the first polarity is the same as the polarity of the second clock edge. 
     
     
       14. A method according to  claim 12 , wherein the first polarity is the same as the polarity of the first clock edge.