Electrostatic discharge circuit and method

Abstract

A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive.

1. An integrated circuit comprising:
 a shunt structure interposed between a power node and a ground node; 
 first circuit operative during a power up event or during a noise event to render the shunt structure non-conductive for a period of time during the power up event or during the noise event; 
 second circuit operative during an electrostatic discharge (ESD) event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure; and 
 wherein the second circuit comprises an ESD feedback circuit operatively coupled to the first circuit, and comprises ESD control logic that is distinct from the ESD feedback circuit and is operatively coupled to the shunt structure. 
 
     
     
       2. The integrated circuit of  claim 1  wherein the shunt structure is comprised of a transistor and wherein the first circuit comprises a first resistor/capacitor (RC) circuit having a first time constant and the second circuit comprises a second resistor/capacitor (RC) circuit having a second and longer time constant than the first time constant. 
     
     
       3. The integrated circuit of  claim 1  wherein the first circuit is operative to turn on the shunt structure during an ESD condition and wherein the second circuit prevents the shunt structure from turning off for a period of time during the ESD condition. 
     
     
       4. The integrated circuit of  claim 1 , wherein the ESD control logic is distinct and separate from components necessary for the first circuit to render the shunt structure non-conductive. 
     
     
       5. The integrated circuit of  claim 1 , wherein the ESD control logic is disposed electrically between a gate of the shunt structure and a gate of the ESD feedback circuit. 
     
     
       6. The integrated circuit of  claim 1 , wherein the ESD control logic uses a shunt gate voltage as an input and provides an output voltage to the ESD feedback circuit. 
     
     
       7. The integrated circuit of  claim 1 , wherein the second circuit comprises ESD control logic operatively coupled to the ESD feedback circuit to control operation of the ESD feedback circuit based on the operational status of the shunt structure. 
     
     
       8. An integrated circuit comprising:
 a shunt transistor interposed between a power node and a ground node; 
 a first RC circuit coupled to the power node and the ground node; 
 a chain of inverters having a front inverter operatively coupled to the first RC circuit and an end inverter operatively coupled to an input of the shunt transistor; 
 a feedback transistor operatively coupled to an input of the end inverter; 
 ESD control logic comprising:
 a second RC circuit coupled to the power node and the ground node, and 
 control logic operatively coupled to the second RC circuit and to the feedback transistor, the control logic being distinct from the chain of inverters. 
 
 
     
     
       9. The integrated circuit of  claim 8  wherein the ESD control logic comprises:
 a PMOS transistor having a terminal operatively coupled to a gate of the shunt transistor, an input that is operatively coupled to an input of an NMOS transistor and wherein the inputs are operatively coupled to the resistor and capacitor of the second RC circuit; and 
 the NMOS transistor having a terminal operatively coupled to a gate of the feedback transistor. 
 
     
     
       10. The integrated circuit of  claim 8  wherein the control logic comprises:
 a transistor operatively coupled to a terminal of the feedback transistor and having a terminal coupled to the ground node; 
 an inverter having an input terminal operatively coupled to the resistor and capacitor of the second RC circuit, and an output terminal coupled to an input terminal of the transistor. 
 
     
     
       11. The integrated circuit of  claim 8  wherein the control logic comprises:
 an NMOS transistor operatively coupled to a terminal of the feedback transistor and having a terminal coupled to the ground node; 
 an inverter having an input terminal operatively coupled to the resistor and capacitor of the second RC circuit, and an output terminal coupled to an input terminal of the transistor; and 
 a PMOS transistor having a gate coupled to the output of the inverter and to the input of the NMOS transistor, and having a first terminal coupled to the input of the end inverter in the chain of inverters and to the feedback transistor, and a second terminal coupled to the power node. 
 
     
     
       12. The integrated circuit of  claim 8 , wherein the ESD control logic uses a voltage from the second RC circuit as an input to the ESD control logic and provides an output to the feedback transistor. 
     
     
       13. The integrated circuit of  claim 12 , wherein the ESD control logic further uses a voltage from the gate of the shunt transistor as an input. 
     
     
       14. The integrated circuit of  claim 8 , wherein the ESD control logic includes at least one element beyond those elements of the first RC circuit and the chain of inverters. 
     
     
       15. The integrated circuit of  claim 8 , wherein the ESD control logic is operatively coupled to the ESD feedback circuit to control operation of the ESD feedback circuit based on the operational status of the shunt transistor and the second circuit. 
     
     
       16. A device comprising the integrated circuit of  claim 8 . 
     
     
       17. A nontransitory computer readable storage medium comprising executable instructions that when executed cause an integrated circuit design system to layout a circuit that comprises:
 a shunt structure interposed between a power node and a ground node; 
 first circuit operative during a power up event to render the shunt structure non-conductive for a period of time during a power up event or during a noise event; 
 second circuit operative during an electrostatic discharge (ESD) event, to keep the shunt transistor conductive for a period of time to discharge electrostatic energy through the shunt structure; and 
 executable instructions that when executed cause the integrated circuit design system to layout a circuit that comprises an ESD feedback circuit to be operatively coupled to the first circuit, and that comprises ESD control logic that is distinct from the ESD feedback circuit and is operatively coupled to the shunt structure.