LNA circuit for use in a low-cost receiver circuit

Abstract

A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal.

1. A low-noise amplifier (LNA) comprising:
 a first input terminal for receiving a first portion of an input signal, the first input terminal adapted to be DC coupled to a first supply terminal; 
 a second input terminal for receiving a second portion of the input signal, the second terminal adapted to be DC coupled to a second power supply terminal; 
 an output terminal; 
 a first transistor comprising a source coupled to the first input terminal, a gate configured to receive a first direct current (DC) bias signal, a drain coupled to the output terminal; and 
 a second transistor comprising a source coupled to the second input terminal, a gate configured to receive a second DC bias signal, a drain coupled to the output terminal, and 
 wherein the LNA is configured to use source degeneration of the first and second transistors to reduce sensitivity to turn on voltage variations across process corners. 
 
     
     
       2. The LNA of  claim 1 , wherein the first transistor has a first width-to-length ratio;
 wherein the second transistor has a second width-to-length ratio; and 
 wherein the first and second width-to-length ratios are configured to achieve a desired second-order input-referred intercept point (IIP2) performance across process corners. 
 
     
     
       3. The LNA of  claim 1 , further comprising:
 a first inductor including a first terminal coupled to the first supply terminal and a second terminal coupled to the first input terminal; and 
 a second inductor including a first terminal coupled to the second input terminal and a second terminal coupled to the second supply terminal. 
 
     
     
       4. The LNA of  claim 1 , wherein the first and second DC bias signals are configured to control the first and second transistors to allow DC current to flow. 
     
     
       5. The LNA of  claim 1 , further comprising:
 a first resistor including a first resistor terminal coupled to the first input terminal-and a second resistor terminal coupled to the source of the first transistor; and 
 a second resistor including a first resistor terminal coupled to the second input terminal and a second resistor terminal coupled to the source of the second transistor. 
 
     
     
       6. The LNA of  claim 1 , further comprising:
 a third transistor comprising a source coupled to the drain of the first transistor, a gate configured to receive a third DC bias signal, and a drain coupled to the output terminal; and 
 a fourth transistor comprising a source coupled to the second input terminal, a gate configured to receive a fourth DC bias signal, and a drain coupled to the source of the second transistor. 
 
     
     
       7. The LNA of  claim 6 , wherein the first and third transistors are p-channel metal oxide semiconductor (PMOS) devices, and
 wherein the second and fourth transistors are n-channel metal oxide semiconductor (NMOS) devices. 
 
     
     
       8. The LNA of  claim 1 , further comprising:
 a first capacitor a first electrode coupled to the first input terminal, and a second terminal for receiving the input signal; and 
 a second capacitor including a first electrode coupled to the second input terminal, and a second electrode for receiving the input signal. 
 
     
     
       9. A device comprising:
 a first input terminal for receiving a first portion of a radio frequency (RF) signal from a signal source, the first input terminal configured to be DC coupled to a first power supply terminal; 
 a second input terminal for receiving a second portion of the RF signal, the second input terminal to be DC coupled to a second power supply terminal; 
 an output terminal for providing an output signal; and 
 a low-noise amplifier (LNA) circuit comprising: 
 a transistor network including a plurality of transistors arranged in series, the plurality of transistors comprising:
 a first transistor including a source coupled to the first input terminal, a drain coupled to the output terminal, and a gate configured to receive a first direct current (DC) bias signal; 
 a second transistor including a source coupled to the second input terminal, a drain coupled to the output terminal, and a gate configured to receive a second DC bias signal; 
 a third transistor including a gate configured to receive a third DC bias signal, a source coupled to the drain of the first transistor, and a drain coupled to the output terminal; and 
 a fourth transistor including a gate configured to receive a fourth DC bias signal, a source coupled to the drain of the second transistor, and a drain coupled to the output terminal. 
 
 
     
     
       10. The device of  claim 9 , wherein the LNA circuit further comprises:
 a first resistor including a first resistor terminal coupled to the first input terminal and a second resistor terminal coupled to the source of the first transistor; and 
 a second resistor including a first resistor terminal coupled to the second input terminal and a second resistor terminal coupled to the source of the second transistor. 
 
     
     
       11. The device of  claim 9 , further comprising a capacitive circuit coupled to the first input terminal and the second input terminal for providing the RF signal, wherein the capacitive circuit comprises:
 a first capacitor including a first electrode coupled to a node for receiving the RF signal and a second electrode coupled to the first input terminal; and 
 a second capacitor including a first electrode coupled to the node and a second electrode coupled to the second input terminal; 
 wherein the first and second capacitors block flow of DC current from the transistor network to the node and from the source of the first transistor to the source of the second transistor through the capacitive circuit. 
 
     
     
       12. The device of  claim 9 , further comprising:
 a passive mixer circuit coupled to the output terminal. 
 
     
     
       13. The device of  claim 9 , further comprising:
 a mixer circuit coupled to the output terminal; and 
 a tunable band-pass inductive/capacitive (LC) filter and a capacitive attenuator network coupled between the output terminal and the mixer circuit. 
 
     
     
       14. The device of  claim 9 , wherein the first and third transistors comprise p-channel metal oxide semiconductor (PMOS) transistors; and
 wherein the second and fourth transistors comprise n-channel metal oxide semiconductor (NMOS) transistors. 
 
     
     
       15. The device of  claim 9 , further comprising:
 a first inductor including a first terminal coupled to a first supply terminal and a second terminal coupled to the source of the first transistor for supplying a DC current; and 
 a second inductor including a first terminal coupled to a second supply terminal and a second terminal coupled to the source of the second transistor. 
 
     
     
       16. The device of  claim 9 , wherein a first portion of the RF signal flows through a first signal path and the first transistor to the output terminal; and
 wherein a second portion of the RF signal flows through a second signal path and the second transistor to the output terminal. 
 
     
     
       17. The device of  claim 9 , further comprising a capacitive circuit including an input terminal for receiving the RF signal, a first output terminal coupled to the first input terminal for providing the first portion of the RF signal, and a second output terminal coupled to the second input terminal for providing the second portion of the RF signal. 
     
     
       18. A low-noise amplifier (LNA) circuit comprising:
 a first input terminal for receiving a first portion of a radio frequency (RF) input signal; 
 a second input terminal for receiving a second portion of the RF input signal; 
 an output terminal for providing an output signal representing an amplified version of the RF input signal; 
 a p-channel metal oxide semiconductor (PMOS) network coupled to the first input terminal and to the output terminal, the PMOS network configured to amplify a first portion of the RF input signal to provide a first amplified portion to the output terminal, the PMOS network comprising: 
 a first PMOS transistor including a source coupled to the first input terminal, the gate configured to receive a first direct current (DC) bias signal, and a drain; and 
 a second PMOS transistor including a source coupled to the drain of the first PMOS transistor, a gate configured to receive a third DC bias signal, and a drain coupled to the output terminal; and 
 an n-channel metal oxide semiconductor (NMOS) network coupled to the second input terminal and to the output terminal and coupled in series with the PMOS network, the NMOS network including at least one control terminal for receiving a second DC bias signal and configured to amplify a second portion of the RF input signal to provide a second amplified portion to the output terminal. 
 
     
     
       19. The LNA circuit of  claim 18 , wherein the NMOS network comprises:
 a first NMOS transistor including a source coupled to the second input terminal, a gate configured to receive the second direct current (DC) bias signal, and a drain; and 
 a second NMOS transistor including a source coupled to the first NMOS drain, a gate configured to receive a fourth DC bias signal, and a drain coupled to the output terminal. 
 
     
     
       20. The LNA circuit of  claim 19 , further comprising:
 a first resistor including a first resistor terminal coupled to the first input terminal and a second resistor terminal coupled to the source of the first PMOS transistor; and 
 a second resistor including a first resistor terminal coupled to the second input terminal and a second resistor terminal coupled to the source of the first NMOS transistor. 
 
     
     
       21. The LNA circuit of  claim 20 , further comprising:
 a first inductor including a first inductive terminal coupled to a first supply terminal and a second inductive terminal coupled to the first resistor terminal of the first resistor; and 
 a second inductor including a first inductive terminal coupled to a second supply terminal and a second inductive terminal coupled to the first resistive terminal of the second resistor. 
 
     
     
       22. The LNA circuit of  claim 18 , wherein the LNA circuit is configured to use source degeneration of at least one of the PMOS network and the NMOS network to desensitize the LNA circuit to turn on voltage variations across process corners.