Loop filter

Abstract

A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

1. A loop filter, comprising
 a first node configured to receive an input signal to the loop filter, and a second node configured to provide an output signal of the loop filter; 
 a first signal path between the first and second nodes, the first signal path including a cascade arrangement coupled between the first node and the second node, the cascade arrangement including:
 a first circuit having a first capacitor proximate to the second node and configured to generate a zero; 
 a second circuit having a second capacitor proximate to the second node and configured to generate a first pole; and 
 a third circuit between the second circuit and the first node and configured to generate a second pole, the third circuit having a third capacitor, the first capacitor having a first capacitance that is greater than a capacitance of the second and third capacitors. 
 
 
     
     
       2. The loop filter of  claim 1  wherein the first circuit has an impedance that is lower than an impedance of the second circuit and an impedance of the third circuit. 
     
     
       3. The loop filter of  claim 1  wherein the first circuit for generating a zero includes at least a first resistor coupled to the first capacitor. 
     
     
       4. The loop filter of  claim 3  wherein the first resistor and the first capacitor are coupled in series between the second node and a reference node. 
     
     
       5. The loop filter of  claim 3  wherein the second circuit includes the first resistor coupled to the second capacitor, and the third circuit includes at least a second resistor and the third capacitor, with the third capacitor coupled to a reference node and the second resistor coupled between the second circuit and the first node. 
     
     
       6. The loop filter of  claim 1 , further including:
 an n-th circuit structured to generate an additional pole coupled to the first node in the first signal path and including at least an n-th resistor and an n-th capacitor, with the n-th capacitor coupled between the first node and a reference node and the n-th resistor coupled between the third circuit and the first node. 
 
     
     
       7. The loop filter of  claim 1  wherein the second and third circuits are configured such that an input impedance of the second pole is higher than an output impedance of the first pole. 
     
     
       8. The loop filter of  claim 1 , further including at least one transistor circuit that includes at least a first transistor having a control node and a controlled path, with the control node of the first transistor coupled to the first node and the controlled path of the first transistor coupled to the second node to form a second signal path that is in parallel to the first signal path. 
     
     
       9. The loop filter of  claim 8  wherein the at least one transistor circuit includes at least a second transistor having a control node and a controlled path, with the control node of the second transistor coupled to the first node and the controlled path of the second transistor coupled to the second node, wherein the first and second transistors are of opposite conductive types. 
     
     
       10. The loop filter of  claim 1 , further comprising:
 a transistor circuit coupled to the second node; and 
 a resistor coupled between the transistor circuit and the second node. 
 
     
     
       11. A loop filter, comprising:
 a first node configured to receive an input signal to the loop filter, and a second node configured to provide an output signal of the loop filter; 
 a first signal path between the first and second nodes that includes a passive filter of at least 3rd order coupled between the first node and the second node, the passive filter including:
 a first circuit between the second node and a reference node and configured to generate a zero, the first circuit having at least a first resistor coupled in series with a first capacitor having a first capacitance; 
 a second circuit configured to generate a first pole and having a second capacitor coupled to the second node and the reference node; and 
 a third circuit between the second circuit and the first node and configured to generate a second pole, the third circuit having a third capacitor coupled between the second circuit and the reference node, and further including a second resistor between the second circuit and the first node, the second and third capacitors each having a capacitance that is less than a capacitance of the first capacitor; and 
 
 at least one transistor circuit coupled to the first node and the second node to constitute a second signal path in parallel to the first signal path. 
 
     
     
       12. The loop filter of  claim 11 , further comprising a third resistor coupled between the second node and the at least one transistor circuit. 
     
     
       13. The loop filter of  claim 12  wherein the at least one transistor circuit includes a pair of transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to the third resistor. 
     
     
       14. A circuit, comprising:
 a loop filter that includes:
 a first node configured to receive an input signal to the loop filter and a second node configured to provide an output signal of the loop filter; 
 a first resistor and first capacitor series coupled between the second node and a reference node and configured to generate a zero; 
 a first circuit configured to generate a first pole, the first circuit including a second capacitor coupled between the second node and the reference node; 
 a second circuit configured to generate a second pole, the second circuit including a third capacitor and including a second resistor having a first terminal connected directly to the second node and having a second terminal; and 
 a third circuit between the second circuit and the first node and configured to generate a third pole and having a third resistor and a fourth capacitor with a first terminal of the fourth capacitor connected directly to the third resistor and with a second terminal connected directly to the reference node, the second, third, and fourth capacitors each having a capacitance that is less than a capacitance of the first capacitor. 
 
 
     
     
       15. The circuit of  claim 14 , comprising a fourth resistor, which has a first terminal coupled to the second node, and at least one transistor circuit having first and second transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to a second terminal of the fourth resistor, and a first one of the two transistors having a second conduction terminal coupled to a voltage source and the other one of the pair of transistors having a second conduction terminal coupled to the reference node. 
     
     
       16. The circuit of  claim 15 , further including:
 a voltage controlled oscillator having an input node coupled to the second node of the loop filter and having an output node; 
 a divider circuit having an input node coupled to the output node of the voltage controlled oscillator and having an output node; 
 a phase detector circuit having an input node coupled to the output node of the divider circuit and having two output nodes; and 
 a charge pump having first and second input nodes coupled to the first and second output nodes of the phase detector circuit and an output node coupled to the first node of the loop filter. 
 
     
     
       17. A phase-locked loop, comprising:
 a phase detector; 
 a charge pump; 
 a voltage controlled oscillator; and 
 a loop filter that includes:
 a first node to provide an input signal to the loop filter, and a second node to provide an output signal of the loop filter; 
 a first signal path between the first and second nodes, the first signal path having a cascade arrangement coupled between the first and second nodes, the cascade arrangement including:
 a first circuit having a first capacitor connected next to the second node and configured to generate a zero; 
 a second circuit having a second capacitor connected next to the second node and configured to generate a first pole; and 
 a third circuit having a third capacitor connected after the second circuit to be closer to the first node than the second circuit and configured to generate a second pole, the second and third capacitors each having a capacitance that is less than a capacitance of the first capacitor. 
 
 
 
     
     
       18. The phase-locked loop of  claim 17 , further comprising at least one transistor circuit coupled to the first node and the second node and configured to constitute a second signal path in parallel to the first signal path, and the at least one transistor circuit including a pair of transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to the second node via a first resistor. 
     
     
       19. The phase-locked loop of  claim 18  wherein the first circuit includes at least a second resistor and the first capacitor coupled in series between the second node and a reference node, and the second circuit includes at least the second capacitor coupled between the second node and the reference node, and the third circuit includes a third resistor having a first terminal coupled to the second node and a second terminal, coupled to a first terminal of the third capacitor, the third capacitor further having a second terminal coupled to the reference node. 
     
     
       20. A loop filter, comprising:
 a first node configured to receive an input signal to the loop filter, and a second node configured to provide an output signal of the loop filter; 
 a cascade arrangement coupled between the first node and the second node to form a first signal path, the cascade arrangement including:
 a first circuit having a first capacitor coupled to the second node and configured to generate a zero; 
 a second circuit having a second capacitor coupled to the second node and configured to generate a first pole; and 
 a third circuit having a third capacitor coupled to the second circuit and configured to generate a second pole; 
 
 at least one transistor circuit coupled to the first node and to the second node to form a second signal path in parallel to the first signal path, the transistor circuit including at least a first transistor having a control node and a controlled path, with the control node of the first transistor coupled to the first node and the controlled path of the first transistor coupled to the second node. 
 
     
     
       21. The loop filter of  claim 20 , further including an n-th circuit structured to generate an additional pole coupled to the first node and including at least an n-th resistor and an n-th capacitor, with the n-th capacitor coupled between the first node and a reference node and the n-th resistor coupled between the third circuit and the first node. 
     
     
       22. The loop filter of  claim 20 , wherein the second and third circuits are configured such that an input impedance of the second pole is higher than an output impedance of the first pole. 
     
     
       23. The loop filter of  claim 20 , wherein the first circuit includes a first resistor and the first capacitor coupled in series between the second node and a reference node, and the third circuit includes a second resistor coupled between the second node and the third capacitor, and further comprising a fourth circuit having a third resistor coupled between the first node and the third circuit and a fourth capacitor coupled between the third resistor and the reference node. 
     
     
       24. A loop filter, comprising:
 a first node configured to receive an input signal to the loop filter, and a second node configured to provide an output signal of the loop filter; 
 a cascade arrangement coupled between the first and second nodes as a first signal path that includes a passive filter of at least 3rd order, the cascade arrangement including:
 a first circuit configured to generate a zero and having at least a first resistor and a first capacitor coupled in series between the second node and a reference node; 
 a second circuit coupled to the second node and having at least a second capacitor coupled between the second node and the reference node; and 
 a third circuit coupled to the first node and having a second resistor and a third capacitor, with the third capacitor coupled to the first node and the reference node and the second resistor coupled between the second circuit and the first node; 
 
 a third resistor coupled to the second node, and 
 at least one transistor circuit coupled to the first node and coupled to the second node via the third resistor and configured as a second signal path in parallel to the first signal path, the at least one transistor circuit having a pair of transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to the third resistor. 
 
     
     
       25. The loop filter of  claim 24 , wherein the second and third circuits are configured such that an input impedance of the second pole is higher than an output impedance of the first pole. 
     
     
       26. A circuit, comprising:
 a loop filter, the loop filter including:
 a first node configured to receive an input signal to the loop filter, a second node configured to conduct an output signal of the loop filter, and a reference node; 
 a first resistor and first capacitor series coupled between the second node and the reference node and configured to generate a zero; 
 a first circuit configured to generate a first pole, the first circuit having a second capacitor that includes a first terminal coupled to the first resistor and to the second node and a second terminal coupled to the reference node; 
 a second circuit configured to generate a second pole, the second circuit having a third capacitor and having a second resistor with a first terminal coupled to the second node and a second terminal coupled to the third capacitor; 
 a third circuit having a fourth capacitor and a third resistor, the fourth capacitor having a first terminal coupled to the first node, and a second terminal coupled to the reference node, and the third resistor coupled between the second resistor and the first node; 
 a fourth resistor having a first terminal coupled to the second node and having a second terminal; and 
 at least one transistor circuit having first and second transistors, each transistor having a gate terminal coupled to the first node and a conduction terminal coupled to the second terminal of the fourth resistor, and a first one of the two transistors having a second conduction terminal coupled to a voltage source and the other one of the pair of transistors having a second conduction terminal coupled to the reference node. 
 
 
     
     
       27. The loop filter of  claim 26 , wherein the second and third circuits are configured such that an input impedance of the second pole is higher than an output impedance of the first pole. 
     
     
       28. The loop filter of  claim 26 , further including:
 a voltage controlled oscillator having an input node coupled to the second node of the loop filter and having an output node; 
 a divider circuit having an input node coupled to the output node of the voltage controlled oscillator and having an output node; 
 a phase detector circuit having an input node coupled to the output node of the divider circuit and having two output nodes; and 
 a charge pump having first and second input nodes coupled to the first and second output nodes of the phase detector circuit and an output node coupled to the first node of the loop filter. 
 
     
     
       29. A phase-locked loop, comprising:
 a phase detector; 
 a charge pump; 
 a voltage controlled oscillator, and 
 a loop filter that includes:
 a first node configured to receive an input signal to the loop filter and a second node configure to conduct an output signal of the loop filter; 
 a cascade arrangement coupled between the first node and the second node to form a first signal path that includes at least a first circuit coupled to the second node and configured to generate a zero, a second circuit coupled to the second node and configured to generate a first pole, and a third circuit coupled to the second circuit and the first node and configured to generate a second pole; 
 a first resistor having a first terminal coupled to the second node, and having a second terminal; and 
 at least one transistor circuit coupled to the first node and the second node to form a second signal path in parallel to the first signal path, the at least one transistor circuit including a pair of transistors, each transistor having a gate terminal coupled to the second node and a conduction terminal coupled to the second terminal of the first resistor. 
 
 
     
     
       30. The circuit of  claim 29 , wherein the voltage controlled oscillator has an input node coupled to the second node of the loop filter and has an output node, the divider circuit has an input node coupled to the output node of the voltage controlled oscillator and has an output node, the phase detector circuit has an input node coupled to the output node of the divider circuit and has two output nodes, and the charge pump has first and second input nodes coupled to the first and second output nodes of the phase detector circuit and an output node coupled to the first node of the loop filter. 
     
     
       31. The loop filter of  claim 29 , wherein the second and third circuits are configured such that an input impedance of the second pole is higher than an output impedance of the first pole.