Split wiper digital potentiometer and method

Abstract

A potentiometer and a method for adjusting an impedance. In accordance with an embodiment, the potentiometer may be a programmable multistage digital potentiometer that has a first stage comprising a non-shunted impedance, a second stage coupled between a reference terminal and the first stage, and a third stage coupled between the first stage and another reference terminal. In accordance with another embodiment, the potentiometer receives a wiper address and parses it into sections such that one section controls the first stage, a second portion controls portions of the second and third stages, and a third portion controls the other portions of the second and third stages to produce a desired impedance between a common wiper terminal and the reference terminals.

1. A potentiometer, comprising:
 first and second reference terminals and a common wiper terminal; 
 a first stage comprising a non-shunted bulk impedance having first and second ends; 
 a second stage comprising first and second impedance structures, the first impedance structure coupled to the first end of the non-shunted bulk impedance and the second impedance structure coupled to the second end of the non-shunted bulk impedance; and 
 a third stage comprising third and fourth impedance structures, the third impedance structure coupled between the first impedance structure and the first reference terminal and the fourth impedance structure coupled between the second impedance structure and the second reference terminal. 
 
     
     
       2. The potentiometer of  claim 1 , wherein the first impedance structure comprises:
 a first impedance element having first and second terminals; 
 a first plurality of switches, each switch of the first plurality of switches having a control terminal and first and second terminals, wherein the first terminal of a first switch of the first plurality of switches is coupled to the first terminal of a second switch of the first plurality of switches, the second terminal of the first switch of the first plurality of switches is coupled to the first terminal of the first impedance element and to the first end of the non-shunted bulk impedance, and the second terminal of the second switch of the first plurality of switches is coupled to the second terminal of the first impedance element. 
 
     
     
       3. The potentiometer of  claim 2 , further including a first wiper switch having a control terminal and first and second terminals, the first terminal coupled to the first terminals of the first and second switches of the first plurality of switches and the second terminal coupled to the common wiper terminal. 
     
     
       4. The potentiometer of  claim 3 , wherein the second impedance structure comprises:
 a second impedance element having first and second terminals; 
 a second plurality of switches, each switch of the second plurality of switches having a control terminal and first and second terminals, wherein the first terminal of a first switch of the second plurality of switches is coupled to the first terminal of a second switch of the second plurality of switches, the second terminal of the first switch of the second plurality of switches is coupled to the first terminal of the second impedance element and to the second end of the non-shunted bulk impedance, and the second terminal of the second switch of the second plurality of switches is coupled to the second terminal of the second impedance element. 
 
     
     
       5. The potentiometer of  claim 4 , further including a second wiper switch having a control terminal and first and second terminals, the first terminal coupled to the first terminals of the first and second switches of the second plurality of switches and the second terminal coupled to the common wiper terminal. 
     
     
       6. The potentiometer of  claim 5 , wherein the third impedance structure comprises:
 a third impedance element having first and second terminals; 
 a third plurality of switches, each switch of the third plurality of switches having a control terminal and first and second terminals, wherein the first terminal of a first switch of the third plurality of switches is coupled to the first terminal of a second switch of the third plurality of switches and to the first reference terminal, the second terminal of the first switch of the third plurality of switches is coupled to the first terminal of the third impedance element, and the second terminal of the second switch of the third plurality of switches is coupled to the second terminal of the third impedance element. 
 
     
     
       7. The potentiometer of  claim 6 , wherein the fourth impedance structure comprises:
 a fourth impedance element having first and second terminals; 
 a fourth plurality of switches, each switch of the fourth plurality of switches having a control terminal and first and second terminals, wherein the first terminal of a first switch of the fourth plurality of switches is coupled to the first terminal of a second switch of the fourth plurality of switches and to the second reference terminal, the second terminal of the first switch of the third plurality of switches is coupled to the first terminal of the fourth impedance element, and the second terminal of the second switch of the fourth plurality of switches is coupled to the second terminal of the fourth impedance element. 
 
     
     
       8. The potentiometer of  claim 1 , wherein the third impedance structure of the third stage further includes a first dummy structure coupled to the first reference terminal. 
     
     
       9. The potentiometer of  claim 1 , wherein the fourth impedance structure of the third stage further includes a first dummy structure coupled to the second reference terminal. 
     
     
       10. The potentiometer of  claim 1 , wherein the first impedance structure comprises:
 a first string of impedance elements, wherein each impedance element of the first string of impedance elements has first and second terminals and wherein a second terminal of a first impedance element is coupled to a first terminal of a second impedance element; and 
 a first plurality of switches wherein each switch of the first plurality of switches has first and second current conducting terminals and a control terminal, a first current conducting terminal of a first switch of the first plurality of switches coupled to the first terminal of the first impedance element, a first current conducting terminal of a second switch of the first plurality of switches coupled to the second terminal of the first impedance element and to the first terminal of the second impedance element and second current conducting terminals of the first and second switches of the first plurality of switches coupled together, the control terminal of the first switch of the first plurality of switches coupled for receiving a first signal and the control terminal of the second switch of the first plurality of switches coupled for receiving a second signal. 
 
     
     
       11. The potentiometer of  claim 10 , wherein the second impedance structure comprises:
 a second string of impedance elements, wherein each impedance element of the second string of impedance elements has first and second terminals and wherein a second terminal of a first impedance element of the second string of impedance elements is coupled to a first terminal of a second impedance element of the second string of impedance elements; and 
 a second plurality of switches wherein each switch of the second plurality of switches has first and second current conducting terminals and a control terminal, a first current conducting terminal of a first switch of the second plurality of switches coupled to the first terminal of the first impedance element of the second string of impedance elements, a first current conducting terminal of a second switch of the second plurality of switches coupled to the second terminal of the first impedance element of the second string of impedance elements and to the first terminal of the second impedance element of the second string of impedance elements, and second current conducting terminals of the first and second switches of the second plurality of switches coupled together, the control terminal of the first switch of the second plurality of switches coupled for receiving a third signal and the control terminal of the second switch of the second plurality of switches coupled for receiving a fourth signal. 
 
     
     
       12. The potentiometer of  claim 11 , wherein the third impedance structure comprises:
 a third string of impedance elements, wherein each impedance element of the third string of impedance elements has first and second terminals and wherein a second terminal of a first impedance element of the third string of impedance elements is coupled to a first terminal of a second impedance element of the third string of impedance elements; and 
 a third plurality of switches, wherein each switch of the third plurality of switches has first and second terminals and a control terminal, a first terminal of a first switch of the third plurality of switches coupled to the second terminal of the first impedance element of the third string of impedance elements, a first terminal of a second switch of the third plurality of switches coupled to the second terminal of the second impedance element of the third string of impedance elements, and second terminals of the first and second switches of the third plurality of switches coupled together, the control terminal of the first switch of the third plurality of switches coupled for receiving a fifth signal, the control terminal of the second switch of the second plurality of switches coupled for receiving a sixth signal, and the first terminal of the first impedance element of the third string of impedance elements coupled to the first reference terminal. 
 
     
     
       13. The potentiometer of  claim 12 , wherein the fourth impedance structure comprises:
 a fourth string of impedance elements, wherein each impedance element of the fourth string of impedance elements has first and second terminals and wherein a second terminal of a first impedance element of the fourth string of impedance elements is coupled to a first terminal of a second impedance element of the fourth string of impedance elements; and 
 a fourth plurality of switches, wherein each switch of the fourth plurality of switches has first and second terminals and a control terminal, a first terminal of a first switch of the fourth plurality of switches coupled to the second terminal of the first impedance element of the fourth string of impedance elements, a first terminal of a second switch of the fourth plurality of switches coupled to the second terminal of the second impedance element of the fourth string of impedance elements, and second terminals of the first and second switches of the fourth plurality of switches coupled together, the control terminal of the first switch of the fourth plurality of switches coupled for receiving a seventh signal, the control terminal of the second switch of the second plurality of switches coupled for receiving an eighth signal, and the first terminal of the first impedance element of the fourth string of impedance elements coupled to the second reference terminal. 
 
     
     
       14. The potentiometer of  claim 13 , further including a first dummy structure coupled between the first terminal of the first impedance element of the third string of impedance elements and the first reference terminal, and a second dummy structure coupled between the first terminal of the first impedance element of the fourth string of impedance elements and the second reference terminal. 
     
     
       15. A method for digitally adjusting an impedance of a potentiometer having 2 n −1 impedance elements coupled between first and second terminals and having 2 n  wiper positions, comprising
 providing an n-bit wiper address; 
 using first and third portions of the n-bit wiper address to control a relative position of a common wiper terminal with respect to two first resolution stages; and 
 using a second portion of the n-bit wiper address to control the relative position of the common wiper terminal with respect to two second resolution stages. 
 
     
     
       16. The method of  claim 15 , wherein:
 using the first portion of the n-bit wiper address comprises using the most significant bit of the n-bit wiper address to control the relative position of the common wiper terminal with respect to the two first resolution stages; 
 using the second portion of the n-bit wiper address comprising using a first plurality of bits of the n-bit wiper address to control the relative position of the common wiper terminal with respect to the two second resolution stages. 
 
     
     
       17. A method for digitally adjusting an impedance of a digital potentiometer having 2 n −1 impedance elements coupled between first and second terminals and having 2 n  wiper positions, comprising:
 providing two first resolution stages, each first resolution stage having first, second, and third terminals, the third terminals of the two first resolution stages coupled together to form a common wiper terminal; 
 providing two second resolution stages, each second resolution stage having first and second terminals, the first terminal of one of the second resolution stages coupled to the first terminal of one of the first resolution stages, and the first terminal of the other second resolution stage coupled to the first terminal of other first resolution stage; 
 providing an impedance stage having first and second terminals, the first and second terminals of the impedance stage coupled to the second terminals of the first resolution stages; 
 using at least one least significant bit and one most significant of an n-bit signal to control the relative position of the common wiper terminal with respect to the first resolution stage; and 
 using a first plurality of bits of the n-bit signal to control the relative position of two common wiper terminals with respect to the second resolution stages. 
 
     
     
       18. A method for digitally adjusting an impedance of a digital potentiometer having 2 n −1 impedance elements coupled between first and second terminals and having 2 n  wiper positions, comprising:
 providing a first resolution stage having first and second terminals; 
 providing a second resolution having first and second terminals, the first terminal of the second resolution stage coupled to the first terminal of the first resolution; 
 using at least one bit and one of an n-bit signal to control the relative position of a common wiper terminal with respect to the first resolution stage; 
 using a first plurality of bits of the n-bit signal to control the relative position of a common wiper terminal with respect to the second resolution stage; and further including providing a third resolution stage having first and second terminals, the first terminal of the third resolution stage coupled to the second terminal of the first resolution stage and using a second plurality of bits of the n-bit signal to control the relative position of the common wiper terminal with respect to the third resolution stage. 
 
     
     
       19. The method of  claim 18 , further including:
 providing a third resolution stage having first and second terminals, the first terminal of the third resolution stage coupled to the second terminal of the first resolution stage and using the first plurality of bits of the n-bit signal to control the relative position of the common wiper terminal with respect to the third resolution stage; 
 providing fourth and fifth resolution stages each having first and second terminals; 
 coupling the first terminal of the fourth resolution stage to the second terminal of the second resolution stage; 
 coupling the first terminal of the fifth resolution stage to the second terminal of the third resolution stage; and 
 using a second plurality of bits of the n-bit signal to control the fourth and fifth resolution stages. 
 
     
     
       20. The method of  claim 19 , wherein the at least one bit is a most significant bit of the n-bit signal, the first plurality of bits comprises at least the least significant bit and the penultimate least significant bits of the n-bit signal, and the second plurality of bits comprises bits of the n-bit signal that are between the most significant bit and the penultimate least significant bit of the n-bit signal. 
     
     
       21. The method of  claim 20 , wherein the second and third resolution stages are substantially the same and the fourth and fifth resolution stages are substantially the same. 
     
     
       22. The method of  claim 21 , wherein the first resolution stage comprises a non-shunted impedance, the second resolution stage comprises a first string of impedances and the third resolution stage comprises a second string of impedances. 
     
     
       23. The method of  claim 22 , further including using first and second switches to select one of the second and fourth resolution stages or the third and fifth resolution stages. 
     
     
       24. The method of  claim 22 , wherein the second resolution stage further includes a first plurality of switches, the third resolution stage further includes a second plurality of switches, the fourth resolution stage further includes a third plurality of switches and the fifth resolution stage further includes a fourth plurality of switches, and further including using the first plurality of bits to control the first plurality of switches and using the second plurality of bits to control the third plurality of switches.