Multi-threshold complementary metal-oxide semiconductor master slave flip-flop

Abstract

A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.

1. A multi-threshold complementary metal-oxide semiconductor, MTCMOS, master slave flip-flop comprising:
 a master storage element comprising low threshold voltage transistors, said master storage element being configured to store an input data in response to a clock signal transition; and 
 a slave storage element comprising high threshold voltage transistors, said slave storage element being configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition, 
 wherein the master and the slave storage elements are provided with a single clock signal, and wherein the master storage element is coupled to an interruptible power supply and the slave storage element is coupled to an always ON power supply, such that the slave storage element is capable of retaining the received data. 
 
     
     
       2. The MTCMOS master slave flip-flop according to  claim 1  wherein:
 the master storage element comprises a first conducting type transistor to be controlled by the single clock signal; and 
 the slave storage element comprises a second conducting type transistor to be controlled by the single clock signal, 
 such that the master storage element is capable to respond to a clock signal transition and the slave storage element is capable to respond to an opposite clock signal transition. 
 
     
     
       3. The MTCMOS master slave flip-flop according to  claim 1  further comprising:
 a first control circuit configured to disconnect the interruptible power supply upon detecting a sleep signal; and 
 a second control circuit configured to provide a predetermined potential to the connection between the master storage element and the slave storage element upon detecting the sleep signal. 
 
     
     
       4. The MTCMOS master slave flip-flop according to  claim 3 , wherein the slave storage element further comprises a retention latch configured to retain the received data and at least one high threshold voltage transistor configured to isolate the retention latch from the rest of the MTCMOS master slave flip-flop upon detecting the predetermined potential provided by the second control circuit. 
     
     
       5. The MTCMOS master slave flip-flop according to  claim 3  wherein the second control circuit provides a low potential to the connection between master storage element and the slave storage element. 
     
     
       6. The MTCMOS master slave flip-flop according to  claim 5  wherein the first control circuit comprises a low threshold voltage transistor and the second control circuit comprises a high threshold voltage transistor. 
     
     
       7. The MTCMOS master slave flip-flop according to  claim 3  further comprising a pass gate capable of interrupting the connection between the master storage element and the slave storage element upon detecting the sleep signal. 
     
     
       8. The MTCMOS master slave flip-flop according to  claim 1  wherein the master storage element comprises a first differential latch and the slave storage element comprises a second differential latch. 
     
     
       9. The MTCMOS master slave flip-flop according to  claim 8  wherein the first differential latch is a static ratio-insensitive differential p-latch and the second differential latch is a static ratio-insensitive differential n-latch. 
     
     
       10. The MTCMOS master slave flip-flop according to  claim 8  wherein the second differential latch comprises at least one clocking transistor with a low threshold voltage. 
     
     
       11. The MTCMOS master slave flip-flop according to  claim 8  further comprising a latching state resetting circuit configured to reset the latching state of the first and of the second differential latch to a predetermined latching state. 
     
     
       12. The MTCMOS master slave flip-flop according to  claim 11  wherein the latching state resetting circuit comprises a low threshold voltage transistor. 
     
     
       13. The MTCMOS master slave flip-flop according to  claim 1  further comprising an input stage configured to control the input of data to the master storage element corresponding to a TE and/or a TI signal. 
     
     
       14. The MTCMOS master slave flip-flop according to  claim 13  wherein the input stage is coupled to an interruptible power supply. 
     
     
       15. The MTCMOS master slave flip-flop according to  claim 1  further comprising an output stage configured to convert the output signal of the slave storage element into a Q and/or a S 0  signal. 
     
     
       16. The MTCMOS master slave flip-flop according to  claim 15  wherein the output stage is coupled to an interruptible power supply. 
     
     
       17. A master slave flip-flop comprising:
 a low threshold master storage element for storing input data in response to a transition of a single clock signal; and 
 a high threshold slave storage element for receiving data from the master storage element and to output the received data in response to an opposite transition of the single clock signal, 
 wherein the master storage element is coupled to an interruptible power supply and the slave storage element is coupled to an always ON power supply, such that the slave storage element is capable of retaining the received data. 
 
     
     
       18. The master slave flip-flop according to  claim 17  wherein:
 the master storage element comprises a cross-coupled latch. 
 
     
     
       19. The master slave flip-flop according to  claim 17  wherein:
 the slave storage element comprises a cross-coupled latch. 
 
     
     
       20. A multi-threshold complementary metal-oxide semiconductor, MTCMOS, master slave flip-flop comprising:
 a master storage element comprising low threshold voltage transistors, said master storage element being configured to store an input data in response to a clock signal transition; and 
 a slave storage element comprising high threshold voltage transistors, said slave storage element being configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition, 
 wherein the master and the slave storage elements are provided with a single clock signal, wherein the master storage element comprises a first differential latch and the slave storage element comprises a second differential latch, and wherein the first differential latch is a static ratio-insensitive differential p-latch and the second differential latch is a static ratio-insensitive differential n-latch. 
 
     
     
       21. A multi-threshold complementary metal-oxide semiconductor, MTCMOS, master slave flip-flop comprising:
 a master storage element comprising low threshold voltage transistors, said master storage element being configured to store an input data in response to a clock signal transition; and 
 a slave storage element comprising high threshold voltage transistors, said slave storage element being configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition, 
 wherein the master and the slave storage elements are provided with a single clock signal, wherein the master storage element comprises a first differential latch and the slave storage element comprises a second differential latch, and wherein the second differential latch comprises at least one clocking transistor with a low threshold voltage.