Semiconductor memory device having a latency controller

Abstract

A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

1. A semiconductor memory device including a latency controller, wherein the latency controller comprising:
 a clock generator configured to generate a plurality of transmission clock signals and to generate a plurality of sampling clock signals, each sampling clock signal delayed for a time corresponding to a set read latency with respect to the corresponding one of the transmission clock signals; 
 a first-in first-out (FIFO) register configured to store an internal read signal in response to at least one sampling clock signal of the sampling clock signals and to generate a latency signal in response to a transmission clock signal corresponding to the sampling clock signal for storing the internal read signal; and 
 a clock blocking unit configured to block application of the sampling clock signal to the FIFO register in response to a power-down signal and to block application of the transmission clock signal to the FIFO register when the power-down signal is applied to the clock blocking unit and a number of times the internal read signal is applied is equal to a number of times the latency signal is applied. 
 
     
     
       2. The device of  claim 1 , wherein the clock blocking unit comprises:
 a power-saving signal generator configured to enable a power-saving command signal when the power-down signal is applied and to enable a power-saving read signal when the power-saving command signal is enabled and a number of times the internal read signal is applied is equal to a number of times the latency signal is applied; 
 a first gate unit including a plurality of sampling switches, each sampling switch configured to block application of the corresponding sampling clock signal to the FIFO register in response to the power-saving command signal; and 
 a second gate unit including a plurality of transmission switches, each transmission switch configured to block application of the corresponding sampling clock signal to the FIFO register in response to the power-saving read signal. 
 
     
     
       3. The device of  claim 2 , wherein the power-saving signal generator enables the power-saving command signal in response to a precharge signal. 
     
     
       4. The device of  claim 3 , wherein the power-saving signal generator comprises:
 a first counter configured to count a number of times the internal read signal is enabled in response to the internal clock signal and to output a first counting value; 
 a second counter configured to count a number of times the latency signal is enabled in response to a data output clock signal and to output a second counting value; 
 a comparator configured to enable an equivalent signal when the first and second counting values are equal; 
 an OR gate configured to perform a logic OR on the precharge signal and the power-down signal and to enable the power-saving command signal; and 
 an AND gate configured to perform a logic AND on the power-saving command signal and the equivalent signal and to enable the power-saving read signal. 
 
     
     
       5. The device of  claim 4 , wherein the FIFO register comprises:
 a plurality of input switches, each input switch configured to transmit the internal read signal in response to the corresponding one of the sampling clock signals applied from the first gate unit; 
 a plurality of buffers, each buffer configured to store the internal read signal applied from the corresponding one of the input switches and to be reset in response to the power-saving read signal; and 
 a plurality of output switches, each output switch configured to receive the stored internal read signal from the corresponding one of the buffers in response to the corresponding one of the transmission clock signals applied from the second gate unit and to output the stored internal read signal as the latency signal. 
 
     
     
       6. The device of  claim 5 , further comprising:
 a memory cell array including a plurality of memory cells interposed between a plurality of word lines and a plurality of bit lines; 
 a row decoder configured to decode a row address and to enable the corresponding one of the word lines; 
 a column decoder configured to decode a column address and to select a predetermined number of bit lines out of the bit lines; 
 a clock synchronous circuit configured to receive an external clock signal and to generate the internal clock signal and the data output clock signal; 
 a command decoder configured to decode an externally applied command and to output the internal read signal, the precharge signal, the power-down signal, and a mode register set (MRS) signal; 
 a mode-setting unit configured to externally receive a mode-setting code in response to the MRS signal and to set the read latency; and 
 a data input/output (I/O) unit configured to output data from the memory cell array, in response to the latency signal. 
 
     
     
       7. The device of  claim 6 , wherein the clock generator comprises:
 a transmission clock generator configured to output the transmission clock signals that sequentially toggle in response to the data output clock signal and the set read latency; 
 a reproduction delay unit configured to receive one of the transmission clock signals, to delay the received transmission clock signal for a time corresponding to the sum of a read delay time and an output delay time, and to output a delay clock signal; and 
 a sampling clock generator including a plurality of sampling flip-flops connected in cascade and configured to sequentially delay the delay clock signal and to output the sampling clock signals in response to the internal clock. 
 
     
     
       8. The device of  claim 7 , wherein the transmission clock generator comprises:
 a plurality of transmission flip-flops connected in cascade, each transmission flip-flop configured to output the corresponding one of the transmission clock signals in response to the data output clock signal; and 
 a plurality of latency switches, each latency switch configured to apply the transmission clock signal, which is applied from the corresponding one of the transmission flip-flops, to a first-stage transmission flip-flop in response to the set read latency. 
 
     
     
       9. The device of  claim 8 , wherein the sampling clock generator includes a plurality of sampling flip-flops connected in cascade and configured to sequentially delay the delay clock signal in response to the internal clock signal and to output the respectively corresponding sampling clock signals. 
     
     
       10. The device of  claim 9 , wherein the sampling clock generator includes the sampling flip-flops provided in a number corresponding to a maximum value of the read latency, and the transmission clock generator includes the transmission flip-flops provided in a number corresponding to the maximum value of the read latency. 
     
     
       11. A semiconductor memory device comprising:
 a memory cell array having a plurality of memory cells interposed between a plurality of word lines and a plurality of bit lines to store data; 
 a data input/output unit coupled to the memory cell array and configured to output data from a memory cell of the memory cell array in response to a read command applied to the semiconductor memory device; and 
 a latency controller for controlling the output of data from the data input/output unit and comprising a first-in first-out register coupled to the data input/output unit, 
 wherein upon the read command being applied to the semiconductor memory device, the latency controller is configured to control the output of data from the data input/output unit by outputting from the first-in first-out register to the data input/output unit a latency signal based upon a set read latency for the semiconductor memory device and corresponding to the applied read command. 
 
     
     
       12. The semiconductor memory device of  claim 11 , wherein the latency controller further comprises:
 a transmission clock signal generator coupled to the first-in first-out register that provides transmission clock signals to the first-in first-out register in response to a data output internal clock signal based upon an external clock signal; and 
 a sampling clock generator coupled to the first-in first-out register that provides sampling clock signals to the first-in first out register in response to a delayed clock signal based upon a delayed first transmission clock signal. 
 
     
     
       13. The semiconductor memory device of  claim 12 , further comprising:
 a first gate unit coupled between the sampling clock generator and the first-in first-out register; and 
 a second gate unit coupled between the transmission clock generator and the first-in first-out register, 
 wherein upon the read command being applied to the semiconductor memory device and in response to a precharge command or a power-down command, the first gate unit is configured to block application of the sampling clock signals to the first-in first-out register and the second gate unit is configured to block application of the transmission clock signals to the first-in first-out register. 
 
     
     
       14. The semiconductor memory device of  claim 12 ,
 further comprising a command decoder for providing an internal read signal to the latency controller based upon the read command, 
 wherein the first-in first-out register is configured to sample the internal read signal and store the sampled signal in response to the sampling clock signals and output the stored sampled signal as the latency signal in response to the transmission clock signals. 
 
     
     
       15. The semiconductor memory device of  claim 12 , wherein the delayed clock signal is delayed by the latency controller for a time corresponding to a set read latency with respect to a corresponding one of the transmission clock signals. 
     
     
       16. The semiconductor memory device of  claim 14 , wherein the first transmission clock signal is delayed by a delay time corresponding to a sum of a read delay time and a data output delay time, the read delay time being a time taken for the command decoder to output the internal read signal in response to the read command, and the data output delay time being a time taken for the data input/output unit to externally output data received from the memory cell array.