P
US8260837B2ExpiredUtilityPatentIndex 77

Handling denormal floating point operands when result must be normalized

Assignee: POWELL JR LAWRENCE JOSEPHPriority: Feb 10, 2005Filed: Sep 22, 2008Granted: Sep 4, 2012
Est. expiryFeb 10, 2025(expired)· nominal 20-yr term from priority
Inventors:POWELL JR LAWRENCE JOSEPHSCHMOOKLER MARTIN STANLEYTRONG SON DAO
G06F 7/49936G06F 7/483
77
PatentIndex Score
9
Cited by
11
References
3
Claims

Abstract

A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Claims

exact text as granted — not AI-modified
1. A system for processing an instruction having denormal floating point operands, comprising:
 a multiplier; 
 first, second and third input lines for inputting a first operand, a second operand, and a third operand of the instruction; 
 an alignment shifter coupled to the second input line; 
 an exponent calculator coupled to the first, second and third input lines, wherein the exponent calculator receives an exponent portion of the first operand, the second operand, and the third operand via the first, second and third input lines; 
 a compare/select unit coupled to the exponent calculator; and 
 a leading zero counter coupled to the second input line and to the compare/select unit, wherein the alignment shifter receives the mantissa of the second operand via the second input line, and wherein: 
 the leading zero counter determines a first shift amount of the mantissa of the second operand based on a number of leading zeros in the mantissa of the second operand, 
 the exponent calculator determines a second shift amount of the mantissa of the second operand based on exponents of the first operand, the second operand, and the third operand, 
 the compare/select unit compares the first shift amount to the second shift amount, 
 the compare/select unit determines if a negative value of the second shift amount is less than the first shift amount, 
 the compare/select unit sets the third shift amount equal to the second shift amount if the negative value of the second shift amount is less than the first shift amount, 
 the compare/select unit sets the third shift amount equal to the first shift amount if the negative value of the second shift amount is not less than the first shift amount, and 
 the alignment shifter shifts the mantissa of the second operand by the third shift amount and the shifted mantissa of the second operand is normalized to generate a normalized result for the instruction, 
 wherein generating a normalized result for the instruction based on the shifted mantissa of the second operand and a product of the first and third operands comprises:
 generating an intermediate result based on the shifted mantissa of the second operand and the product of the first and third operands; 
 generating a normalize shift amount based on the third shift amount, wherein the normalize shift amount is the sum of the third shift amount and the number of leading zeros of the mantissa of the second operand; and 
 
 normalizing the intermediate result based on the normalize shift amount. 
 
     
     
       2. The system of  claim 1 , wherein the instruction is one of a fused-multiply-add and a fused-multiply-subtract instruction. 
     
     
       3. The system of  claim 1 , further comprising:
 a rounder unit; and 
 floating point registers coupled to the rounder unit, wherein the rounder unit receives an intermediate exponent from the exponent calculator and the normalized result and generates a rounded result of the instruction which is provided to the floating point registers.

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