Memory array with metal-insulator transition switching devices

Abstract

A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series with an MIT material. A method of accessing a target memory element within a memory array includes applying half of an access voltage to a row line connected to the target memory element, the target memory element comprising a switching layer in series with an MIT material, and applying an inverted half of the access voltage to a column line connected to the target memory element.

1. A memory array with Metal-Insulator Transition (MIT) switching devices, the memory array comprising:
 a set of row lines intersecting a set of column lines; and 
 a memory element disposed at an intersection between one of said row lines and one of said column lines; 
 in which said memory element comprises a switching layer in series with an MIT material, wherein said switching layer is a memristive switching layer. 
 
     
     
       2. The memory array of  claim 1 , in which said memristive switching layer comprises an intrinsic semiconductor region and a highly doped secondary region. 
     
     
       3. The memory array of  claim 1 , further comprising a voltage supply to apply an access voltage across said memory element. 
     
     
       4. The memory array of  claim 3 , in which said access voltage is one of: a read voltage and a write voltage. 
     
     
       5. The memory array of  claim 3 , in which to apply said access voltage, half of said access voltage is applied to said row line connected to said memory element and an inverted half of said access voltage is applied to said column line connected to said memory element. 
     
     
       6. The memory array of  claim 5 , in which to read a state of said memory element, said half of said access voltage is less than a threshold voltage required to change a state of said switching layer. 
     
     
       7. The memory array of  claim 1 , in which said MIT material comprises at least one of: a vanadium oxide material, a niobium oxide material, an iron oxide material, a manganese oxide material, and a titanium oxide material. 
     
     
       8. A method of accessing a target memory element within a memory array, the method comprising:
 applying half of an access voltage to a row line connected to said target memory element, said target memory element comprising a switching layer in series with a Metal-Insulator Transition (MIT) material; and 
 applying an inverted half of said access voltage to a column line connected to said target memory element. 
 
     
     
       9. The method of  claim 8 , further comprising, detecting the electric current flowing through said target memory element to determine a state of said target memory element. 
     
     
       10. The method of  claim 8 , in which said switching layer is a memristive switching layer. 
     
     
       11. The method of  claim 9 , in which said memristive switching layer comprises an intrinsic semiconductor region and a highly doped secondary region. 
     
     
       12. The method of  claim 8 , in which said access voltage is one of: a read voltage and a write voltage. 
     
     
       13. The method of  claim 8 , in which to read a state of said memory element, said half of said access voltage is less than a threshold voltage required to change a state of said switching layer. 
     
     
       14. The method of  claim 8 , in which said MIT material comprises at least one of: a vanadium oxide material, a niobium oxide material, an iron oxide material, a manganese oxide material, and a titanium oxide material. 
     
     
       15. A memory array comprising:
 addressing circuitry; and 
 a number of memory blocks, at least one of said memory blocks comprising:
 a number of row lines; 
 a number of column lines intersecting said number of row lines; and 
 memory elements disposed at intersections between said column lines and said row lines, said memory elements comprising a switching layer in series with a Metal-Insulator Transition (MIT) material, wherein said switching layer is a memristive switching layer. 
 
 
     
     
       16. The memory array of  claim 15 , in which said memristive switching layer comprises an intrinsic semiconductor region and a highly doped secondary region. 
     
     
       17. The memory array of  claim 15 , further comprising a voltage supply to apply an access voltage to one of said memory elements, said access voltage being one of: a read voltage and a write voltage. 
     
     
       18. The memory array of  claim 17 , in which to apply said access voltage to said one of said memory elements, half of said access voltage is applied to one of said row lines connected to said one of said memory elements and an inverted half of said access voltage is applied to one of said column lines connected to said one of said memory elements. 
     
     
       19. The memory array of  claim 15 , in which said MIT material comprises at least one of: a vanadium oxide material, a niobium oxide material, an iron oxide material, a manganese oxide material, and a titanium oxide material.