Information processing apparatus and control method therefor

Abstract

This invention provides an information processing apparatus which shortens the memory access time and reduces the cost while ensuring data reliability. To accomplish this, the information processing apparatus shifts each write start timing so that data to be written in at least one memory is not influenced by noise during write when writing the same information in a plurality of memories. When reading data from a plurality of memories, the information processing apparatus compares the data with each other to estimate normal data.

1. An information processing apparatus comprising:
 a plurality of storage units including a first storage unit, a second storage unit, and a third storage unit; 
 a writing unit configured to write same data in said plurality of storage units, wherein the writing unit writes a first part of the data in a first part of the first storage unit at a first timing, writes a second part of the data in a second part of the first storage unit and the first part of the data in a first part of the second storage unit at a second timing which is later than the first timing, writes the second part of the data in a second part of the second storage unit and the first part of the data in a first part of the third storage unit at a third timing which is later than the second timing, and writes the second part of the data in a second part of the third storage unit at a fourth timing which is later than the third timing; 
 a reading unit configured to read a plurality of data written in said plurality of storage units; and 
 an estimation unit configured to estimate normal data based on the plurality of data read by said reading unit when data of at least one combination out of the plurality of data read by said reading unit are determined not to match each other. 
 
     
     
       2. The apparatus according to  claim 1 , wherein when data of only some combinations are determined not to match each other, said estimation unit estimates that matched data of a combination are the normal data. 
     
     
       3. The apparatus according to  claim 1 , wherein when data of all combinations are determined not to match each other, said estimation unit estimates that combined data obtained by extracting only valid bits from respective data and combining the valid bits is the normal data. 
     
     
       4. The apparatus according to  claim 3 , further comprising:
 a comparison unit configured to compare two data to determine whether the two data match each other by exclusive-ORing the two data for all the combinations; 
 a counting unit configured to, when the two selected data are compared, count the number of mismatch bits among all bits of the compared data; 
 a valid higher-order bit extraction unit configured to search a combination having a largest number of mismatch bits from a lower-order bit of a comparison result by said comparison unit, specify, as valid bits, bits of higher order than a bit at which the number of occurrence of mismatch bits becomes smaller by one than the number of mismatch bits, and extract the valid bits of data written first when writing data in said storage units; 
 a valid lower-order bit extraction unit configured to search a combination having a largest number of mismatch bits from a higher-order bit of a comparison result by said comparison unit, specify, as valid bits, bits of lower order than a bit at which the number of occurrence of mismatch bits becomes smaller by one than the number of mismatch bits, and extract the valid bits of data written later when writing the data in said storage units; and 
 a combination unit configured to combine, into one data, the valid bits extracted by said valid higher-order bit extraction unit and said valid lower-order bit extraction unit, 
 wherein when the combined data matches the data having the smallest number of mismatches generated, the combined data is estimated to be the normal data, and 
 wherein when the combined data does not match the data having the smallest number of mismatches generated, an error process is executed by reason of normal data is not obtained. 
 
     
     
       5. The apparatus according to  claim 1 , wherein said writing unit changes a timing by starting write of data in each storage unit with a shift of a predetermined time. 
     
     
       6. The apparatus according to  claim 5 , wherein when data includes N (N is a natural number) bits, the predetermined time is a time necessary to write N/2+1 bits in said storage unit. 
     
     
       7. The apparatus according to  claim 1 , further comprising a restore unit configured to restore data by writing the estimated normal data again in each storage unit by said writing unit. 
     
     
       8. A method of controlling an information processing apparatus having a plurality of storage units including a first storage unit, a second storage unit, and a third storage unit, the method comprising the steps of:
 writing a first part of the data in a first part of the first storage unit at a first timing, writing a second part of the data in a second part of the first storage unit and the first part of the data in a first part of the second storage unit at a second timing which is later than the first timing, writing the second part of the data in a second part of the second storage unit and the first part of the data in a first part of the third storage unit at a third timing which is later than the second timing, and writing the second part of the data in a second part of the third storage unit at a fourth timing which is later than the third timing; 
 reading a plurality of data written in the plurality of storage units; and 
 estimating normal data based on the plurality of data read from the plurality of storage units when data of at least one combination out of the plurality of data read from the plurality of storage units are determined not to match each other. 
 
     
     
       9. The method according to  claim 8 , wherein in the step of estimating normal data, when data of only some combinations are determined not to match each other, matched data of a combination are estimated to be the normal data. 
     
     
       10. The method according to  claim 8 , wherein in the step of estimating normal data, when data of all combinations are determined not to match each other, combined data obtained by extracting only valid bits from respective data and combining the valid bits is estimated to be the normal data. 
     
     
       11. The method according to  claim 10 , further comprising:
 comparing two data to determine whether the two data match each other by exclusive-ORing the two data for the all combinations; 
 when the two selected data are compared, counting the number of mismatch bits among all bits of the compared data; 
 searching a combination having a largest number of mismatch bits from a lower-order bit of a comparison result in the step of comparing two data to determine whether the two data match each other, specifying, as valid bits, bits of higher order than a bit at which the number of occurrence of mismatch bits becomes smaller by one than the number of mismatch bits, and extracting the valid bits of data written first when writing data in the storage units; 
 searching a combination having a largest number of mismatch bits from a higher-order bit of a comparison result in the step of comparing two data to determine whether the two data match each other, specifying, as valid bits, bits of lower order than a bit at which the number of occurrence of mismatch bits becomes smaller by one than the number of mismatch bits, and extracting the valid bits of data written later when writing data in the storage units; and 
 combining, into one data, the valid bits extracted in the step of extracting higher-order bits and the step of extracting lower-order bits, 
 wherein when the combined data is determined to match the data having the smallest number of mismatches generated, the combined data is estimated to be the normal data, and 
 wherein when the combined data is determined not to match the data having the smallest number of mismatches generated, an error process is executed by reason of normal data is not obtained. 
 
     
     
       12. The method according to  claim 8 , wherein in the step of writing data in each storage unit, a timing is changed by starting write of data in each storage unit with a shift of a predetermined time. 
     
     
       13. The method according to  claim 12 , wherein when data includes N (N is a natural number) bits, the predetermined time is a time necessary to write N/2+1 bits in the storage unit. 
     
     
       14. The method according to  claim 8 , further comprising the step of restoring data by writing the estimated normal data again in each storage unit in the step of writing data in each storage unit.