DLL phase detection using advanced phase equalization

Abstract

A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit. The avoidance of wrong ForceSL exit and On1x overshooting problems further results in faster DLL locking time.

1. A method of operating a synchronous circuit, comprising:
 applying a reference clock as an input to a delay line to obtain a feedback clock at an output of said delay line; and 
 obtaining a first delayed feedback clock by delaying said feedback clock by a first delay only during a shift mode in which a delay of the delay line is forced to change in only one direction; 
 obtaining a second delayed feedback clock from said feedback clock; and 
 when not in the shift mode, generating a shift signal to control the delay of said delay line based on a relationship among the respective phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock. 
 
     
     
       2. The method of  claim 1 , wherein obtaining said second delayed feedback clocks includes:
 delaying said first feedback clock with a second delay to obtain said second delayed feedback clock. 
 
     
     
       3. The method of  claim 2 , further comprising:
 delaying said reference clock with a third delay to obtain a delayed reference clock, 
 and wherein generating said shift signal comprises generating said shift signal based on a relationship among the respective phases of said delayed reference clock, said first delayed feedback clock, and said second delayed feedback clock. 
 
     
     
       4. The method of  claim 3 , wherein the amount of said third delay is half of the amount of said second delay. 
     
     
       5. The method of  claim 3 , further comprising:
 sampling said first delayed feedback clock at a rising edge of said delayed reference clock to generate a first logic value; 
 sampling said second delayed feedback clock at said rising edge of said delayed reference clock to generate a second logic value; and 
 delaying said feedback clock by a first delay in the upon initialization of said synchronous circuit only as long as both of said first and said second logic values are both the same. 
 
     
     
       6. The method of  claim 5 , further comprising:
 terminating the shift mode to terminate the delay of said feedback clock by a first delay responsive to an occurrence of said second logic value becoming different than said first logic value. 
 
     
     
       7. The method of  claim 5 , wherein generating said shift signal comprises generating said shift signal to increase the delay of said delay line upon initialization of said synchronous circuit so long as both of said first and said second logic values are the same. 
     
     
       8. The method of  claim 7 , further comprising:
 discontinuing said shift signal responsive to an occurrence of said second logic value becoming different than said first logic value. 
 
     
     
       9. The method of  claim 1 , wherein the delay of the delay line is forced to change in a direction so as to increase the amount of delay imparted by said delay line during the shift mode. 
     
     
       10. A method of operating a synchronous circuit, comprising:
 delaying a reference clock to obtain a feedback clock; 
 during an initialization mode of said synchronous circuit, forcing the delay of said reference clock to change in only one direction regardless of the respective relationships among the phases of said reference clock and said feedback clock; 
 delaying said feedback clock to obtain a first delayed feedback clock only during said initialization mode; 
 at a conclusion of said initialization mode, discontinuing delaying said feedback clock to obtain said first delayed feedback clock; 
 obtaining a second delayed feedback clock from said feedback clock; and 
 at a conclusion of said initialization mode, controlling the delay of said reference clock to obtain said feedback clock based on a relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock. 
 
     
     
       11. The method of  claim 10 , further comprising:
 determining a phase relationship between said reference clock and said first delayed feedback clock by sampling said first delayed feedback clock with said reference clock; and 
 continuing said initialization mode so long as a first phase relationship between said reference clock and said first delayed feedback clock is determined to exist. 
 
     
     
       12. A method of operating a synchronous circuit, comprising:
 delaying a reference clock to provide a feedback clock; 
 during an initialization mode, delaying said feedback clock by a first delay to obtain a first delayed feedback clock; 
 during the initialization mode, obtaining a second delayed feedback signal by delaying the first delayed feedback signal; 
 when not in the initialization mode, obtaining the second delayed feedback signal by delaying the feedback signal; 
 during the initialization mode, changing the delay of the reference clock in a first direction to provide the feedback clock regardless of respective relationships among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock; and 
 when not in the initialization mode, controlling the delay of the reference clock to provide the feedback clock based on a relationship among the phases of said reference clock, said feedback clock, and said second delayed feedback clock. 
 
     
     
       13. The method of  claim 12 , further comprising:
 sampling said first delayed feedback clock using said reference clock to generate a first logic value; 
 further sampling said second delayed feedback clock using said reference clock to generate a second logic value; and 
 continuing the initialization mode so long as both of said first and said second logic values are the same. 
 
     
     
       14. The method of  claim 13 , further comprising:
 discontinuing the initialization mode responsive to said second logic value becoming different from said first logic value. 
 
     
     
       15. A method, comprising:
 obtaining a reference clock; 
 generating a feedback clock from said reference clock, wherein frequencies of said feedback clock and said reference clock are identical; 
 obtaining a first delayed feedback clock and a second delayed feedback clock from said feedback clock; 
 advancing or retarding a timing of said feedback clock relative to said reference clock based on a relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock; 
 entering a first mode to force said feedback clock to be delayed by a delay equal to a feedback path delay relative to said reference clock regardless of the relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock; 
 entering a second mode to further delay said feedback clock relative to said reference clock on each clock cycle of said reference clock regardless of the relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock; 
 monitoring the relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock after entering said first and said second modes; and 
 exiting said first and said second modes based on a phase relationship between said reference clock and said first delayed feedback clock. 
 
     
     
       16. The method of  claim 15  wherein said exiting comprises:
 exiting said first mode when a first phase relationship between said reference clock and said first delayed feedback clock has a first logic value and a second phase relationship between said reference clock and said second delayed feedback clock reaches a second logic value for the first time; and 
 exiting said second mode when said first phase relationship has said first logic value and said second phase relationship again reaches said second logic value. 
 
     
     
       17. The method of  claim 15  wherein said exiting comprises:
 exiting said first and said second modes when a first phase relationship between said reference clock and said first delayed feedback clock has a first logic value and a second phase relationship between said reference clock and said second delayed feedback clock reaches a second logic value. 
 
     
     
       18. The method of  claim 15  wherein said obtaining a first delayed feedback clock and a second delayed feedback clock comprises:
 selecting said feedback clock that is delayed by a first delay relative to said reference clock during a first shift mode and selecting said feedback clock that bypasses said first delay during when said first mode is not active. 
 
     
     
       19. A synchronous circuit, comprising:
 a delay line for receiving a reference clock and for generating a feedback clock therefrom; and 
 a phase detector coupled to said delay line for receiving said feedback clock and for generating a first delayed feedback clock and a second delayed feedback clock from the feedback clock, wherein said phase detector is configured to also receive said reference clock and to generate a shift signal based on a relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock, wherein said phase detector is further configured to input said shift signal to said delay line so as to enable said delay line to shift said reference clock to increase or decrease the delay based on said shift signal, said phase detector comprising a controlled delay unit configured to select between applying a delay unit to said feedback clock to generate said first delayed feedback clock during a shift mode where the reference clock is forced to shift in only one direction and bypassing said delay unit during an operation mode where the reference clock is not forced to shift in only said one direction to generate said first delayed feedback clock. 
 
     
     
       20. The circuit of  claim 19 , wherein said phase detector further comprises:
 a first reference clock delay unit to provide a first delay to said reference clock, thereby generating a delayed reference clock; and 
 another delay unit to provide a third delay to said first delayed feedback clock, thereby generating said second delayed feedback clock. 
 
     
     
       21. The circuit of  claim 20 , wherein said delay of said first reference clock delay unit is half of said delay of said another delay unit. 
     
     
       22. The circuit of  claim 20 , wherein said delay of said first reference clock delay unit and said delay of said another delay unit are fixed, and wherein said delay of said delay unit is variable. 
     
     
       23. The circuit of  claim 20 , wherein said controlled delay unit is configured to receive said feedback clock and a control signal as inputs thereto and for generating said first delayed feedback clock at an output thereof, wherein said second delay unit includes a plurality of delay units, and wherein said controlled delay unit is configured to apply said feedback clock to said second delay unit when said control signal is active, and wherein said controlled delay unit is further configured to prevent application of said feedback clock to said second delay unit when said control signal is inactive. 
     
     
       24. The circuit of  claim 19 , wherein said phase detector further comprises:
 a first sampler circuit for sampling said first delayed feedback clock using said reference clock, thereby generating a first phase relation signal; 
 a second sampler circuit for sampling said second delayed feedback clock using said delayed reference clock, thereby generating a second phase relation signal; and 
 a shift signal generator coupled to said first and said second sampler circuits for generating said shift signal from said first and said second phase relation signals. 
 
     
     
       25. The circuit of  claim 24 , wherein said phase detector further comprises:
 a control unit coupled to said shift signal generator for receiving said first and said second phase relation signals and for generating a control signal therefrom; and 
 wherein said controlled delay unit is configured to receive said control signal and is further configured to receive said feedback clock from said delay line, wherein said controlled delay unit is configured to apply said second delay unit to said feedback clock to generate said first delayed feedback clock when said control signal is active, and to bypass said second delay unit to generate said first delayed feedback clock when said control signal is inactive. 
 
     
     
       26. The circuit of  claim 25 , wherein said control unit is configured to generate said control signal upon initialization of said synchronous circuit, and wherein said control circuit is further configured to terminate generation of said control signal when said first phase relation signal has a first logic value and said second phase relation, signal achieves a different logic value for the first time after said initialization of said synchronous circuit. 
     
     
       27. The circuit of  claim 25 , wherein said control unit is configured to generate said control signal upon initialization of said synchronous circuit, and wherein said phase detector is configured to supply said control signal to said delay line upon said initialization so as to enable said delay line to shift said reference clock in one direction regardless of the relationship among the phases of said reference clock, said first delayed feedback clock, and said second delayed feedback clock. 
     
     
       28. A combination, comprising:
 a plurality of memory cells for storing data; and 
 a delay locked loop configured to provide a clock signal to facilitate a data read/write operation at one or more of said plurality of memory cells, wherein said delay locked loop comprises:
 a delay line for receiving a reference clock and for generating said clock signal therefrom, and 
 a phase detector coupled to said delay line for receiving said clock signal and for generating a first delayed clock and a second delayed clock therefrom, wherein said phase detector is configured to also receive said reference clock and to generate a shift signal based on a relationship among the phases of said reference clock, said first delayed clock, and said second delayed clock, wherein said phase detector is further configured to input said shift signal to said delay line so as to enable said delay line to shift said reference clock leftward or rightward based on said shift signal, said phase detector comprising a controlled delay unit configured to select between applying a delay unit to said feedback clock to generate said first delayed feedback clock during a shift mode where the reference clock is forced to shift in only one direction and bypassing said delay unit during an operation mode where the reference clock is not forced to shift in only said one direction to generate said first delayed feedback clock. 
 
 
     
     
       29. A system, comprising:
 a processor; 
 a bus; and 
 a memory device coupled to said processor via said bus, wherein said memory device comprises: 
 a synchronous circuit having: 
 a delay line for receiving a reference clock and for generating a feedback clock therefrom, and 
 a phase detector coupled to said delay line for receiving said feedback clock and for generating a first delayed clock and a second delayed clock therefrom, wherein said phase detector is configured to also receive said reference clock and to generate a shift signal based on a relationship among the phases of said reference clock, said first delayed clock, and said second delayed clock, wherein said phase detector is further configured to input said shift signal to said delay line so as to enable said delay line to shift said reference clock leftward or rightward based on said shift signal, said phase detector comprising a controlled delay unit configured to select between applying a delay unit to said feedback clock to generate said first delayed feedback clock during a shift mode where the reference clock is forced to shift in only one direction and bypassing said delay unit during an operation mode where the reference clock is not forced to shift in only said one direction to generate said first delayed feedback clock.