Thin film transistor substrate and method of manufacturing the same

Abstract

A thin film transistor substrate capable of appropriately maintaining driving performance even when there is a difference between manufacturing processes and a method of manufacturing the same. The thin film transistor substrate includes: a gate electrode formed on an insulating substrate; a semiconductor layer formed on the gate electrode; and a plurality of thin film transistors each having a source electrode and a drain electrode that are formed on the gate electrode and the semiconductor layer so as to be spaced apart from each other. At least one of the plurality of thin film transistors is a dummy thin film transistor that does not have the semiconductor layer between the source electrode and the drain electrode.

1. A thin film transistor substrate comprising:
 a gate electrode formed on an insulating substrate; 
 a semiconductor layer formed on the gate electrode; and 
 a gate driver comprising a plurality of thin film transistors each having a source electrode and a drain electrode that are formed on the gate electrode and the semiconductor layer so as to be spaced apart from each other, 
 wherein at least one of the plurality of thin film transistors include the gate electrode and has a gap between the source electrode and the drain electrode, and the gap is directly on the gate electrode. 
 
     
     
       2. The thin film transistor substrate of  claim 1 , wherein about 20 to 60% of the plurality of thin film transistors are the at least one of the plurality of thin film transistors. 
     
     
       3. The thin film transistor substrate of  claim 1 , further comprising a shift register having a plurality of stages connected to each other in a cascade manner and being formed on the insulating substrate, each of the stages including:
 a pull-up unit outputting a first clock signal as a gate signal in response to the signal of a first node to which a first input signal is input; 
 a pull-down unit discharging the gate signal with an off voltage when receiving a second input signal; 
 a discharge unit discharging the signal of the first node with the off voltage in response to the second input signal; and 
 a holding unit holding the signal of the first node as the gate signal discharged with the off voltage in response to the first clock signal, 
 wherein one or more of the thin film transistors among the plurality of thin film transistors are configured to control the operation of respective stages of the plurality of stages. 
 
     
     
       4. The thin film transistor substrate of  claim 3 , wherein each of the plurality of thin film transistors has the gate electrode to which the first clock signal is supplied, the drain electrode connected to the first node, and the source electrode connected to a gate line. 
     
     
       5. A thin film transistor substrate comprising:
 a gate electrode formed on an insulating substrate; 
 a semiconductor layer formed on the gate electrode; and 
 a plurality of thin film transistors each having a source electrode and a drain electrode formed on the gate electrode and the semiconductor layer so as to be spaced apart from each other and having a respective channel, 
 a shift register having a plurality of stages connected to each other in a cascade manner and being formed on the insulating substrate, 
 wherein each of the stages include:
 a pull-up unit outputting a first clock signal as a gate signal in response to the signal of a first node to which a first input signal is input; 
 a pull-down unit discharging the gate signal with an off voltage when receiving a second input signal; 
 a discharge unit discharging the signal of the first node with the off voltage in response to the second input signal; and 
 a holding unit holding the signal of the first node as the gate signal discharged with the off voltage in response to the first clock signal and including the plurality of thin film transistors; 
 
 wherein one or more of the thin film transistors among the plurality of thin film transistors are configured to control the operation of respective stages of the plurality of stages, and 
 wherein one or more of the thin film transistors among the plurality of thin film transistors have different channel lengths. 
 
     
     
       6. The thin film transistor substrate of  claim 5 , wherein each of the plurality of thin film transistors has the gate electrode to which the first clock signal is supplied, the drain electrode connected to the first node, and the source electrode connected to a gate line.