Semiconductor memory device

Abstract

A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

1. A semiconductor memory device comprising:
 a sensing and amplifying unit configured to sense and amplify data inputted through a first bit line and an additional bit line connected to a second bit line; and 
 a loading unit connected to the first bit line and configured to have a loading value corresponding to the additional bit line. 
 
     
     
       2. The semiconductor memory device of  claim 1 , further comprising:
 a first sub memory cell area including the first bit line; and 
 a second sub memory cell area including the second bit line, 
 wherein the first sub memory cell area and the second sub memory cell area are arranged in a stacking structure. 
 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the loading unit is connected to the first bit line in a memory cell mat disposed at an edge. 
     
     
       4. The semiconductor memory device of  claim 1 , further comprising:
 a first switching unit configured to form a data transfer path of the first bit line and the sensing and amplifying unit; and 
 a second switching unit connected to the additional bit line and configured to form a data transfer path of the second bit line and the sensing and amplifying unit through the additional bit line. 
 
     
     
       5. The semiconductor memory device of  claim 4 , wherein the first switching unit and the second switching unit are activated at the same time in response to a control signal. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein the loading unit includes a capacitor.