Memory chip architecture having non-rectangular memory banks and method for arranging memory banks

Abstract

A semiconductor memory device having semiconductor memory chips, each semiconductor memory chip includes a plurality of memory banks capable of independently to be accessed, each memory bank having a plurality of memory blocks, wherein at least two memory blocks, which are neighbored each other in the same memory bank, have the different number of unit memory blocks, so that each bank has a non-rectangular shape.

1. A semiconductor memory device comprising:
 a plurality of memory banks capable of independently being accessed, each memory bank having a plurality of memory blocks, wherein each memory bank has a non-rectangular shape; and 
 a plurality of pads and control blocks arranged in a vacant space formed between neighboring memory banks, 
 wherein at least two of the plurality of memory blocks, which are adjacent each other in the same memory bank, have different numbers of unit memory blocks, and wherein the non-rectangular shapes of the plurality of memory banks are arranged to be symmetric about a longitudinal axis of a semiconductor chip passing between the plurality of memory banks, or about a latitudinal axis of the semiconductor chip passing between the plurality of the memory banks. 
 
     
     
       2. The semiconductor memory device as recited in  claim 1 , wherein each of the plurality of memory blocks includes a pair of X-decoder and Y-decoder capable of accessing one or more unit memory blocks within a memory block. 
     
     
       3. The semiconductor memory device as recited in  claim 1 , wherein a total memory region of the semiconductor memory chip is divided into four memory banks, wherein the four memory banks are arranged in the first, second, third and fourth quadrants of the semiconductor memory chip, respectively. 
     
     
       4. The semiconductor memory device as recited in  claim 3 , wherein each memory bank includes:
 a first memory block having a first number of the unit memory blocks; 
 a second memory block having a second number of the unit memory blocks, which is smaller than that of the first memory blocks; and 
 a third memory block having the second number of unit memory blocks. 
 
     
     
       5. The semiconductor memory device as recited in  claim 4 , wherein the first memory blocks of memory banks arranged in the second and third quadrants are arranged at a left-most region of the semiconductor memory chip and the first memory block of banks arranged in the first and fourth quadrants is arranged at a right-most region of the semiconductor memory chip. 
     
     
       6. The semiconductor memory device as recited in  claim 1 , wherein the entire outer shape of the plurality of banks including the plurality of pads and control blocks is a rectangular shape. 
     
     
       7. The semiconductor memory device as recited in  claim 1 , wherein the plurality of memory blocks comprises a first memory block having a first number of unit memory blocks and a second memory block having a second number of unit memory blocks less than the first number of unit memory blocks; and
 wherein the vacant space is formed corresponding to a difference region between the first memory block and the second memory block. 
 
     
     
       8. The semiconductor memory device as recited in  claim 1 , wherein the non-rectangular shapes of the plurality of memory banks are arranged to be symmetric about a longitudinal axis of the semiconductor chip passing between the plurality of memory banks, and about a latitudinal axis of the semiconductor chip passing between the plurality of the memory banks. 
     
     
       9. The semiconductor memory device as recited in  claim 1 , wherein one half of the plurality of memory banks is located on a first side of the longitudinal axis, and one half of the plurality of memory banks is located on a second side of the longitudinal axis, opposite the first side. 
     
     
       10. The semiconductor memory device as recited in  claim 9 , wherein one half of the plurality of memory banks is located on a first side of the latitudinal axis, and one half of the plurality of memory banks is located on a second side of the latitudinal axis, opposite the first side.