Device, method, and protocol for data transfer between host device and device having storage interface

Abstract

A system for transferring data files between a host device and a secondary device can include a bridge device forming at least a portion of the secondary device. The bridge device can have a de-multiplex (de-MUX) data path with an input coupled to a host interface (I/F), a first output coupled to a storage I/F and a second output coupled to a processor I/F. A controller circuit can have control inputs coupled to receive configuration commands from the processor I/F and control outputs coupled to control terminals of the de-MUX data path. The controller circuit enables and maintaining a data path between the host I/F and the first output of the de-MUX data path for a predetermined number of data transfers in response to at least a first configuration data input.

1. A system for transferring data files between a host device and a secondary device, comprising:
 a bridge device forming at least a portion of the secondary device, the bridge device including
 a de-multiplex (de-MUX) data path with an input coupled to a host interface (I/F), a first output coupled to a storage I/F and a second output coupled to a processor I/F, and 
 a controller circuit having at least control inputs coupled to receive configuration commands from the processor I/F and control outputs coupled to the de-MUX data path, the controller circuit enabling and maintaining a data path between the host I/F and the first output of the de-MUX data path for a predetermined number of data transfers in response to at least a first configuration data input. 
 
 
     
     
       2. The system of  claim 1 , further including:
 at least a first buffer circuit having locations for storing data values, the at least first buffer being coupled to the de-MUX path and 
 a first interface circuit coupled to the first buffer circuit that selectively provides an input path between the host I/F and the first buffer circuit. 
 
     
     
       3. The system of  claim 2 , wherein:
 the first buffer circuit comprises a first-in-first-out memory. 
 
     
     
       4. The system of  claim 1 , wherein:
 the bridge device further includes
 a multiplex (MUX) data path with an output coupled to the host I/F, a first input coupled to the storage I/F and a second input coupled to the processor I/F, and 
 the controller circuit further having control outputs coupled to the MUX data path, the controller circuit enabling and maintaining a data path between the host I/F and the first input of the MUX data path for a predetermined number of data transfers in response to a second configuration data input. 
 
 
     
     
       5. The system of  claim 4 , further including:
 at least a second buffer circuit having locations for storing data values, the at least second buffer circuit being coupled to the MUX data path, and 
 a second interface circuit coupled to the second buffer circuit that selectively provides an output path between the storage I/F and the second buffer circuit. 
 
     
     
       6. The system of  claim 1 , wherein:
 the controller circuit further comprises a plurality of registers, and 
 the de-MUX data path is coupled to receive configuration data from at least one of the registers. 
 
     
     
       7. The system of  claim 1 , wherein:
 the host I/F comprises a serial interface circuit that receives data in a serial format and outputs such data in parallel; and 
 the processor I/F comprises a parallel interface circuit that input and outputs data values in parallel. 
 
     
     
       8. A system for transferring data files between a host device and a secondary device, the system comprising:
 the secondary device comprising,
 a bridge device coupled between a processor interface (I/F), a storage I/F and a host I/F, the bridge device configurable to provide a control path between the host I/F and the processor and a data path between the host I/F and the storage I/F in response to at least one predetermined command from the processor I/F, the data path bypassing the processor I/F, the bridge device also being coupled to receive file system information from the processor I/F, the file system information organizing data files accessed via the storage I/F. 
 
 
     
     
       9. The system of  claim 8 , wherein:
 bridge device comprises
 an input de-multiplexer (de-MUX) path having at least a first input coupled to the host I/F, and 
 an output multiplexer (MUX) path having at least a first output coupled to the host I/F. 
 
 
     
     
       10. The system of  claim 9 , wherein:
 the input de-MUX path further includes a second output coupled to the processor and first output coupled to the storage I/F, and 
 the output MUX path further includes a second input coupled to the processor and first input coupled to the storage I/F. 
 
     
     
       11. The system of  claim 10 , wherein:
 the bridge device further includes a buffer circuit coupled between the host I/F and the input de-MUX path. 
 
     
     
       12. The system of  claim 10 , further including:
 a processor coupled to the processor I/F configured to directly access a file system that organizes data files accessed via the storage interface (I/F). 
 
     
     
       13. The system of  claim 12 , including:
 at least one storage device coupled to the storage I/F, wherein the storage I/F is configurable to automatically transfer data from the bridge device to the at least one storage device without storing the data at any memory location of the processor. 
 
     
     
       14. A method of transferring data between a host device and a secondary device, the method comprising:
 in response to a predetermined command received by a bridge device of the secondary device, from a processor interface (I/F), using a controller circuit of the bridge device:
 providing a control path to transfer control information from a host I/F to a processor I/F; and 
 enabling and maintaining a data path between the host I/F and a first output of a de-MUX data path for a predetermined number of data transfers to transfer data from the host I/F to a storage I/F, the data path bypassing the processor I/F; and 
 
 receiving file system information from the processor I/F, the file system information organizing data files accessed via the storage I/F. 
 
     
     
       15. The method of  claim 14 , wherein:
 the predetermined command is a data phase of a three phase protocol that includes an operation request phase, a data transfer phase, and an operation acknowledgement phase. 
 
     
     
       16. The method of  claim 15 , wherein:
 in the data transfer phase of the protocol
 data payload information is transmitted in a first packet and the data payload is transmitted in at least one subsequently transmitted packet. 
 
 
     
     
       17. The method of  claim 14 , wherein:
 the using of the controller circuit of the bridge device to provide the control path and the data path includes receiving control information from the processor I/F indicating a configuration of at least the data path. 
 
     
     
       18. The method of  claim 14 , further including:
 the secondary device includes at least one data endpoint that indicates at least a logical destination for data received by the secondary device; and 
 not acknowledging host device accesses to the at least one endpoint while a processor accesses the at least one endpoint via the processor I/F. 
 
     
     
       19. The method of  claim 14 , further including:
 storing packet data received from the host device in a first endpoint buffer; 
 in a first configuration, transferring the packet data to the processor I/F via a first route of an input de-MUX path; and 
 in a second configuration resulting from the predetermined command, transferring the packet data to the storage I/F via a second route of the input de-MUX path. 
 
     
     
       20. The method of  claim 19 , further including:
 in the first configuration, transferring packet data received from the processor I/F via a first route of an output MUX into a second endpoint buffer; and 
 in the second configuration resulting from the predetermined command, transferring packet data received from the storage I/F via a second route of the output MUX into the second endpoint buffer.