Process for manufacturing an integrated device with “damascene” field insulation, and integrated device made by such process

Abstract

An integrated device includes a semiconductor body, in which an STI insulation structure is formed, which delimits laterally first active areas and at least one second active area, respectively, in a low-voltage region and in a power region of the semiconductor body. The integrated device moreover includes low-voltage CMOS components, accommodated in the first active areas, and a power component in the second active area. The power component has a source region, a body region, a drain-contact region, and at least one field-insulating region, set between the body region and the drain-contact region. The field-insulating region is provided entirely on the semiconductor body.

1. A semiconductor device, comprising:
 a drain region; 
 a body region disposed in the drain region; 
 a source region disposed in the body region; 
 a gate insulator disposed over the body region; 
 a gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region and disposed over the gate insulator. 
 
     
     
       2. The semiconductor device of  claim 1  wherein:
 the gate insulator is disposed over the drain region; and 
 the isolation region is disposed over the gate insulator. 
 
     
     
       3. The semiconductor device of  claim 1  wherein the gate region is in contact with the isolation region. 
     
     
       4. The semiconductor device of  claim 1  wherein the gate region is disposed over the isolation region. 
     
     
       5. The semiconductor device of  claim 1  wherein the gate region is laterally adjacent to the isolation region. 
     
     
       6. The semiconductor device of  claim 1 , further comprising:
 a semiconductor layer;
 wherein the drain region is disposed in the semiconductor layer; and 
 
 a second isolation region disposed in the semiconductor layer and laterally adjacent to the drain region. 
 
     
     
       7. The semiconductor device of  claim 1 , further comprising:
 a semiconductor layer;
 wherein the drain region is disposed in the semiconductor layer; and 
 
 a silicon-trench isolation region disposed in the semiconductor layer and laterally adjacent to the drain region. 
 
     
     
       8. The semiconductor device of  claim 1  wherein:
 the drain region has an N-type conductivity; 
 the body region has a P-type conductivity; and 
 the source region has an N-type conductivity. 
 
     
     
       9. A semiconductor device, comprising:
 a drain region; 
 a body region disposed in the drain region; 
 a source region disposed in the body region; 
 a gate insulator disposed over the body region; 
 a gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; 
 further comprising a contact region disposed in the source region. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein the contact region disposed in the source region extends to the body region. 
     
     
       11. A semiconductor device, comprising:
 a drain region; 
 a body region disposed in the drain region; 
 a source region disposed in the body region; 
 a gate insulator disposed over the body region; 
 a gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; 
 further comprising a contact region disposed in the drain region. 
 
     
     
       12. A semiconductor device, comprising:
 a drain region; 
 a body region disposed in the drain region; 
 a source region disposed in the body region; 
 a gate insulator disposed over the body region; 
 a gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; 
 wherein: 
 the drain region has a P-type conductivity; 
 the body region has an N-type conductivity; and 
 the source region has a P-type conductivity. 
 
     
     
       13. An integrated circuit, comprising:
 a semiconductor layer; 
 a first drain region disposed in the layer; 
 a first body region disposed in the drain region; 
 a first source region disposed in the body region; 
 a first gate insulator disposed over the body region; 
 a first gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region and over the gate insulator. 
 
     
     
       14. The integrated circuit of  claim 13 , further comprising a second isolation region disposed in the semiconductor layer and laterally adjacent to the drain region. 
     
     
       15. An integrated circuit, comprising:
 a semiconductor layer; 
 a first drain region disposed in the layer; 
 a first body region disposed in the drain region; 
 a first source region disposed in the body region; 
 a first gate insulator disposed over the body region; 
 a first gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; 
 
       further comprising:
 a second body region disposed in the layer; 
 a second drain region disposed in the second body region; 
 a second source region disposed in the second body region; 
 a second gate insulator disposed over the second body region; 
 a second gate region disposed over the second gate insulator; and 
 a second isolation region disposed in the semiconductor layer between the first drain region and the second body region. 
 
     
     
       16. A system, comprising:
 a first integrated circuit including a device that includes:
 a first drain region; 
 a first body region disposed in the drain region; 
 a first source region disposed in the body region; 
 a first gate insulator disposed over the body region; 
 a first gate region disposed over the gate insulator; and 
 a first isolation region disposed over and separated from the drain region; and 
 
 a second integrated circuit coupled to the first integrated circuit. 
 
     
     
       17. The system of  claim 16  wherein the first and second integrated circuits are disposed on a same die. 
     
     
       18. The system of  claim 16  wherein the device comprises a power transistor. 
     
     
       19. The system of  claim 16  wherein the device comprises a lateral power transistor. 
     
     
       20. A system, comprising:
 a first integrated circuit including a device that includes:
 a first drain region; 
 a first body region disposed in the drain region; 
 a first source region disposed in the body region; 
 a first gate insulator disposed over the body region; 
 a first gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; and 
 
 a second integrated circuit coupled to the first integrated circuit; 
 wherein the first and second integrated circuits are disposed on respective dies. 
 
     
     
       21. A system, comprising:
 a first integrated circuit including a device that includes:
 a first drain region; 
 a first body region disposed in the drain region; 
 a first source region disposed in the body region; 
 a first gate insulator disposed over the body region; 
 a first gate region disposed over the gate insulator; and 
 a first isolation region disposed over the drain region; and 
 
 a second integrated circuit coupled to the first integrated circuit; 
 wherein the one of the first and second integrated circuit circuits comprises a controller. 
 
     
     
       22. A semiconductor device, comprising:
 a drain region; 
 a body region disposed in the drain region; 
 a source region disposed in the body region; 
 a gate insulator disposed over the body region; 
 a gate region disposed over the gate insulator; and 
 a first isolation region disposed over and separated from the drain region.