System and method for providing a low-power self-adjusting reference current for floating supply stages

Abstract

A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

1. A system comprising:
 a first section, comprising:
 a first simple current reference; 
 an accurate current reference; and 
 a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference; and 
 
 a second section, comprising:
 a second simple current reference providing a second reference current; 
 an adjustment circuit providing an adjustment current based upon the digital error signal; and 
 a circuit having a biasing equivalent to a summation of the second reference current and the adjustment current. 
 
 
     
     
       2. The system of  claim 1 , wherein the first simple current reference and the second simple current reference are equivalent circuits. 
     
     
       3. The system of  claim 1 , wherein the accurate current reference can be generated on chip or externally. 
     
     
       4. The system of  claim 1 , wherein the circuit that generates a digital error signal further comprises:
 at least one transistor branch, each transistor branch having a node wherein a voltage at the node is selected based upon a difference between the output of the first simple current reference and the output of the accurate current reference. 
 
     
     
       5. The system of  claim 4 , wherein the voltage at the node corresponds to a bit in the digital error signal. 
     
     
       6. The system of  claim 1 , wherein the circuit that generates a digital error signal further comprises:
 a digital level shifter; and 
 a memory element. 
 
     
     
       7. The system of  claim 1 , wherein the adjustment circuit further comprises:
 at least one transistor branch, each transistor branch having a switch controlled by one bit in the digital error signal. 
 
     
     
       8. The system of  claim 7 , wherein, in an ON state, the at least one transistor branch provides at least a portion of the adjustment current. 
     
     
       9. A system for providing a correction signal for a reference current, comprising:
 a first circuit providing a first reference current; 
 a second circuit providing a second reference current, the second circuit requiring more power than the first circuit; 
 at least one branch circuit, each branch circuit comprising a node wherein a voltage at the node is dependent upon a difference between the first reference current and the second reference current; and 
 an output circuit that provides a digital signal comprising bits that are proportional to voltages at the nodes of respective ones of the branch circuits. 
 
     
     
       10. The system of  claim 9 , wherein the output circuit is a digital level shifter circuit, and wherein a number of bits in the digital signal corresponds to a number of branch circuits. 
     
     
       11. The system of  claim 9 , wherein the output circuit further comprises a memory element for storing the digital signal. 
     
     
       12. A system for providing an adjusted reference current, comprising:
 a current mirror circuit comprising a first mirror transistor and a second mirror transistor, the second mirror transistor providing current to an output circuit; 
 a reference branch drawing a reference current; 
 a plurality of adjustment branches, each adjustment branch providing an adjustment current, the adjustment branches controlled by switching one of the transistors; 
 wherein the current through the first mirror transistor equals the reference current plus adjustment currents for any active adjustment branches. 
 
     
     
       13. The system of  claim 12 , further comprising:
 a memory element circuit storing a digital signal, wherein bits in the digital signal are used to switch transistors in the adjustment branches. 
 
     
     
       14. The system of  claim 13 , wherein the current provided to the output circuit by the second mirror transistor is equal to the reference current plus adjustment currents for any active adjustment branches. 
     
     
       15. The system of  claim 14 , wherein the adjustment branches are activated when a corresponding bit in the digital signal has been set. 
     
     
       16. The system of  claim 12 , wherein the output circuit is any stage which needs a biasing current. 
     
     
       17. A method for providing an adjusted reference current, comprising:
 generating a first reference current; 
 generating a second reference current; 
 driving first transistors in a plurality of reference branch circuits using the first reference current; 
 driving second transistors in the plurality of reference branch circuits using the second reference current; 
 detecting voltage levels at nodes between the first transistors and second transistors on each of the reference branch circuits; 
 storing the voltage levels as digital bits; 
 switching first transistors in a plurality of adjustment branch circuits using the digital bits, wherein each of the adjustment branch circuits is switched On/Off by a different digital bit; 
 drawing a first mirror current through a first mirror transistor, the first mirror current equal to a third reference current plus adjustment currents generated in active ones of the adjustment branch circuits, the third reference current equal to the first reference current; 
 drawing a second mirror current through a second mirror transistor, the second mirror current equal to the first mirror current; and 
 driving an output circuit using the second mirror current. 
 
     
     
       18. The method of  claim 17 , wherein the digital bits are stored in a memory element circuit. 
     
     
       19. The method of  claim 17 , wherein the third reference current is equivalent to the first reference current.