Programmable vias for structured ASICs

Abstract

A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

1. A semiconductor device comprising:
 a number of metal layers having vias formed among and between them; 
 a further metal layer overlying an uppermost metal layer of the number of metal layers; 
 a via layer between the further metal layer and the uppermost metal layer, the via layer comprising one or more programmable vias between one or more segments of the uppermost metal layer and the further metal layer, said one or more programmable vias comprising at least one material having a changeable resistance, wherein the at least one material having a changeable resistance is configured to have its resistance changed by passing an electric signal through the at least one material and at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       2. The semiconductor device according to  claim 1 , further comprising:
 a first shift register to address said programmable vias; and 
 a second shift register to address said programmable vias, 
 wherein the first and second shift registers are to be programmed with data to specify a set of said programmable vias. 
 
     
     
       3. The semiconductor device according to  claim 2 , further comprising:
 one or more transistors, each coupled to either the first shift register or the second shift register, to provide electric current across one or more of said set of said programmable vias. 
 
     
     
       4. A semiconductor device comprising:
 a number of metal layers having vias formed among and between them; 
 a further metal layer overlying an uppermost metal layer of the number of metal layers; 
 a via layer between the further metal layer and the uppermost metal layer, the via layer comprising one or more programmable vias between one or more segments of the uppermost metal layer and the further metal layer, said one or more programmable vias comprising at least one material having a changeable resistance, wherein the at least one material having a changeable resistance is configured to have its resistance changed by exposure to multiple focused laser beams and at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       5. The semiconductor device according to  claim 1 , further comprising:
 one or more buffers inserted at one or more points to limit a number of vias in high-resistance states that are connected to a particular metal segment. 
 
     
     
       6. A semiconductor device comprising:
 a number of metal layers having vias formed among and between them; 
 a further metal layer overlying an uppermost metal layer of the number of metal layers; 
 a via layer between the further metal layer and the uppermost metal layer, the via layer comprising one or more programmable vias between one or more segments of the uppermost metal layer and the further metal layer, said one or more programmable vias comprising at least one material having a changeable resistance; and 
 at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       7. A method of fabricating a semiconductor device, the method comprising:
 forming a number of metal layers having vias formed among and between them; 
 forming a via layer on top of an uppermost one of the number of metal layers, said via layer being formed using at least one material having a changeable resistance; 
 forming a further metal layer on top of said via layer, wherein said via layer is adapted to provide at least one programmable via between said uppermost metal layer and said further metal layer, wherein the at least one material having a changeable resistance is configured to have its resistance changed by passing an electric signal through the at least one material and forming at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       8. A method of fabricating a semiconductor device; the method comprising:
 forming a number of metal layers having vias formed among and between them; 
 forming a via layer on top of an uppermost one of the number of metal layers, said via layer being formed using at least one material having a changeable resistance; 
 forming a further metal layer on top of said via layer, wherein said via layer is adapted to provide at least one programmable via between said uppermost metal layer and said further metal layer, wherein the at least one material having a changeable resistance is configured to have its resistance changed by exposure to multiple focused laser beams and forming at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       9. The method according to  claim 7 , further comprising:
 forming at least a first shift register and a second register coupled to said via layer to enable programming of one or more vias of said via layer. 
 
     
     
       10. The method according to  claim 9 , further comprising:
 forming one or more transistors, each coupled to either the first shift register, or the second shift register and also coupled to a via of said via layer. 
 
     
     
       11. The method according to  claim 7 , further comprising:
 forming one or more buffers at one or more points, the points located in said uppermost metal layer, said further metal layer, or both, to limit a number of vias in high-resistance states that are connected to a particular metal segment. 
 
     
     
       12. A method of fabricating a semiconductor device, the method comprising:
 forming a number of metal layers having vias formed among and between them; 
 forming a via layer on top of an uppermost one of the number of metal layers, said via layer being formed using at least one material having a changeable resistance; 
 forming a further metal layer on top of said via layer, wherein said via layer is adapted to provide at least one programmable via between said uppermost metal layer and said further metal layer; and 
 forming at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state. 
 
     
     
       13. A method of using a programmable semiconductor device, the semiconductor device including a number of metal layers having interconnections among and between them, a via layer including at least one programmable via formed from at least one material having a changeable resistance and being formed atop an uppermost one of the number of metal layers, and a further metal layer on top of said programmable via layer, and at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state, the method comprising:
 programming said at least one programmable via of said via layer to selectively form at least one connection between segments of said uppermost metal layer and said further metal layer or to electrically isolate at least one segment of said uppermost metal layer and at least one segment of said further metal layer, wherein said programming comprises passing an electric signal through at least one programmable via of said via layer to change its resistance. 
 
     
     
       14. The method according to  claim 13 , wherein said programming further comprises:
 changing a temperature of at least one programmable via of said via layer. 
 
     
     
       15. A method of using a programmable semiconductor device, the semiconductor device including a number of metal layers having interconnections among and between them, a via layer including at least one programmable via formed from at least one material having a changeable resistance and being formed atop an uppermost one of the number of metal layers, and a further metal layer on top of said programmable via layer, and at least one pass transistor or at least one tri-state buffer coupled to a metal segment, the metal segment having high-resistance-state vias coupled to power and to ground, wherein the at least one pass transistor or at least one tri-state buffer is configured to mitigate at least one negative effect of finite resistance of one or more of the programmable vias when one or more of the one or more programmable vias is in a high-resistance state, the method comprising:
 programming said at least one programmable via of said via layer to selectively form at least one connection between segments of said uppermost metal layer and said further metal layer or to electrically isolate at least one segment of said uppermost metal layer and at least one segment of said further metal layer, wherein said programming comprises exposing at least one programmable via of said via layer to a laser beam to change its resistance, wherein said exposing comprises using multiple focused beams to provide energy to a particular via location.