Programmable analog tile configuration tool

Abstract

A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

1. A method comprising:
 (a) communicating a power management control characteristic query; 
 (b) receiving, by using a computer, a user response to the query from across a network; 
 (c) generating tile configuration information based at least in part on the user response of (b), wherein the tile configuration information is to configure a first power management integrated circuit tile of an integrated circuit by storing the tile configuration information in configuration registers in the first power management integrated circuit tile; 
 (d) arranging a first position of the first power management integrated circuit tile with respect to a second position of a second power management integrated circuit tile and a third position of a third power management integrated circuit tile in the integrated circuit; and 
 (e) communicating the tile configuration information from the first power management integrated circuit tile, through the second power management integrated circuit tile, to the third power management circuit tile. 
 
     
     
       2. The method of  claim 1 , wherein the power management control characteristic query includes a query for a clocking frequency value. 
     
     
       3. The method of  claim 1 , wherein the power management control characteristic query includes a query for a switching frequency value. 
     
     
       4. The method of  claim 1 , wherein the power management control characteristic query includes a query for a tile output voltage. 
     
     
       5. The method of  claim 1 , wherein the power management control characteristic query includes a query for a tile output current. 
     
     
       6. The method of  claim 1 , wherein (a) involves a serving of a webpage, wherein the power management control characteristic query is a part of the webpage. 
     
     
       7. The method of  claim 1 , wherein the network is the Internet. 
     
     
       8. The method of  claim 1 , wherein the first power management integrated circuit tile includes a first bus portion, wherein the second power management integrated circuit tile includes a second bus portion, further comprising:
 (f) arranging the first power management integrated circuit tile and the second power management integrated circuit tile to be disposed adjacent to one another in the integrated circuit such that the first bus portion and the second bus portion connect to form a standardized bus. 
 
     
     
       9. The method of  claim 8 , further comprising:
 (g) transmitting the tile configuration information to the first power management integrated circuit tile over the standardized bus. 
 
     
     
       10. The method of  claim 1 , wherein the first power management integrated circuit tile taken from the group consisting of: a buck converter tile, a boost converter tile, a low dropout regulator tile, a linear regulator tile, a battery charger tile, a charge pump tile, a battery and power path management tile, a switching power controller tile, and a lighting control module tile. 
     
     
       11. The method of  claim 1 , wherein the generating tile configuration information is performed by a computer. 
     
     
       12. The method of  claim 1 , wherein each of the configuration registers includes at least one electrically programmable non-volatile bit. 
     
     
       13. The method of  claim 1 , wherein the tile configuration information includes at least one bit value for determining a tile output voltage. 
     
     
       14. The method of  claim 1 , wherein the tile configuration information includes at least one bit value for determining a tile output current capability. 
     
     
       15. The method of  claim 1 , wherein the tile configuration information includes an address of at least one of the configuration registers. 
     
     
       16. A non-transitory processor-readable medium storing a set of processor-executable instructions, the instructions when executed by a processor, performing:
 (a) sending a power management control characteristic query across a network so that the power management control characteristic query can be displayed to a user; 
 (b) receiving a user response to the query from across the network; and 
 (c) generating tile configuration information based at least in part on the user response of (b), wherein the tile configuration information is to configure a first power management integrated circuit tile by storing the tile configuration information in configuration registers in the first power management integrated circuit tile; 
 (d) arranging a first position of the first power management integrated circuit tile with respect to a second position of a second power management integrated circuit tile and a third position of a third power management integrated circuit tile in the integrated circuit; and 
 (e) communicating the tile configuration information from the first power management integrated circuit tile, through the second power management integrated circuit tile, to the third power management circuit tile. 
 
     
     
       17. An apparatus comprising:
 a network port; and 
 a processor configured to: 
 communicate a power management control characteristic query; 
 receive a user response to the query from across a network via the network port; 
 generate tile configuration information based at least in part on the user response, wherein the tile configuration information is to configure a first power management integrated circuit tile of an integrated circuit by storing the tile configuration information in configuration registers in the first power management integrated circuit tile; 
 arrange a first position of the first power management integrated circuit tile with respect to a second position of a second power management integrated circuit tile and a third position of a third power management integrated circuit tile in the integrated circuit; and 
 communicate the tile configuration information from the first power management integrated circuit tile, through the second power management integrated circuit tile, to the third power management circuit tile. 
 
     
     
       18. The apparatus of  claim 17 , wherein the user response to the query is received from across the network.