Flat panel display

Abstract

A high-speed flat panel display has thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, which have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One thin film transistor has a zigzag shape in its gate region or drain region or has an offset region.

1. A flat panel display, comprising:
 a pixel array portion having a plurality of pixels arranged thereon; and 
 a gate driving circuit portion and a data driving circuit portion for driving the plurality of pixels of the pixel array portion, 
 wherein a first semiconductor layer of at least one thin film transistor of thin film transistors in the pixel array portion has a first region between its drain region and its source region, the first region being asymmetric with respect to its channel region, and the first region has a different shape, when viewed from above perpendicular to the flat panel display, from a second region of a second semiconductor layer of at least one thin film transistor of thin film transistors in the gate driving circuit portion and thin film transistors in the data driving circuit portion, the second region being disposed between a source region and a drain region of the second semiconductor layer. 
 
     
     
       2. The flat panel display according to  claim 1 , wherein the first semiconductor layer includes an offset region. 
     
     
       3. The flat panel display according to  claim 2 , wherein the offset region has a zigzag shape. 
     
     
       4. The flat panel display according to  claim 2 , wherein the width of the offset region varies from the drain region to the source region. 
     
     
       5. A flat panel display, comprising:
 a pixel array portion having a plurality of pixels arranged thereon; and 
 a gate driving circuit portion and a data driving circuit portion for driving the plurality of pixels of the pixel array portion, 
 wherein at least one thin film transistor of thin film transistors in the pixel array portion has a different geometric structure from at least one thin film transistor of thin film transistors in the gate driving circuit portion and thin film transistors in the data driving circuit portion, 
 wherein the at least one thin film transistor of the thin film transistors in the pixel array portion includes an offset region in one of its gate region and its drain region, and 
 wherein the offset region of the at least one thin film transistor in the pixel array portion has at least one of a longer length and a shorter width than those of the other thin film transistors.