Critical-path circuit for performance monitoring

Abstract

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

1. An integrated circuit having a monitor circuit for monitoring timing in a critical path in the integrated circuit, the critical path having a target timing margin, the monitor circuit comprising:
 a first shift register having an input and an output, the first shift register including a delay circuit that applies a delay value to a received signal; 
 a second shift register having an input and an output, wherein the inputs of the first and second shift registers are connected together to form a signal input node capable of receiving an input signal; and 
 a logic circuit having an output and at least two inputs, each input connected to a corresponding one of the outputs of the first and second shift registers, wherein the output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied, wherein:
 the first shift register comprises:
 a first flip-flop having an input connected to the signal input node and an output; 
 the delay circuit connected to the output of the first flip-flop, and 
 a second flip-flop having an input connected to the delay circuit; and 
 
 the second shift register comprises:
 a third flip-flop having an input connected to the signal input node and an output; and 
 a fourth flip-flop having an input connected to the output of the third flip-flop; and 
 
 the delay circuit comprises:
 a gross-delay element adapted to provide a gross delay value; and 
 a fine-delay detector circuit adapted to generate, based on the gross delay value, an output signal indicating the extent to which the target timing margin is satisfied. 
 
 
 
     
     
       2. The integrated circuit of  claim 1 , wherein:
 if the delay value is less than a predetermined period of time plus the target timing margin, then the logic circuit produces an output indicating that the target timing margin has been satisfied, and 
 if the delay value is greater than the predetermined period of time plus the target timing margin, then the logic circuit produces an output indicating that the target timing margin has not been satisfied. 
 
     
     
       3. The integrated circuit of  claim 2 , wherein, if an input pulse is inserted at the signal input node, then:
 (i) the first shift register produces a first pulse at its output; 
 (ii) the second shift register produces a second pulse at its output; and 
 (iii) the logic circuit produces an output indicating that the target timing margin has not been satisfied only if the first pulse is separated in time from the second pulse by an amount of time more than the predetermined period of time plus the target timing margin. 
 
     
     
       4. The integrated circuit of  claim 1 , wherein the logic circuit is one of an XOR logic gate and an NXOR logic gate. 
     
     
       5. The integrated circuit of  claim 1 , further comprising a pulse generator adapted to provide the input signal at an output connected to the signal input node. 
     
     
       6. The integrated circuit of  claim 1 , wherein the monitor circuit is (i) substantially independent of the critical path and (ii) located sufficiently near the critical path to be monitored in the integrated circuit such that an indication that the target timing margin has not been satisfied indicates that a timing problem exists in the critical path. 
     
     
       7. The integrated circuit of  claim 1 , wherein the fine-delay detector circuit comprises:
 a delay line having an input and a plurality of delay-line elements connected in series, each delay-line element having an input and an output. 
 
     
     
       8. The integrated circuit of  claim 7 , wherein the fine-delay detector circuit further comprises:
 a plurality of flip-flops, one or more flip-flops having an input and an output, the input of each being connected to the input of a corresponding delay-line element, wherein:
 the outputs of the plurality of flip-flops indicate the extent to which the target timing margin is satisfied. 
 
 
     
     
       9. The integrated circuit of  claim 8 , wherein the fine-delay detector circuit further comprises:
 a plurality of logic gates, each logic gate having at least two inputs respectively connected to the outputs of a corresponding pair of adjacent flip-flops in the plurality of flip-flops in series along the delay line, wherein:
 the output of at least one logic gate indicates the extent to which the target timing margin is satisfied. 
 
 
     
     
       10. The integrated circuit of  claim 1 , wherein the first shift register comprises a first plurality of shift elements, and the second shift register comprises a second plurality of shift elements. 
     
     
       11. A method for monitoring timing in a critical path in an integrated circuit, the critical path having a target timing margin, the method comprising:
 (a) splitting an input signal into a first path including a first shift register and a second path including a second shift register; 
 (b) delaying the input signal in the first path by a first delay; 
 (c) comparing the input signal in the second path with the delayed input signal in the first path; 
 (d) producing, based on the comparison, an output indicating whether the target timing margin is satisfied or not satisfied: and 
 (e) detecting the extent to which the target timing margin is satisfied or not satisfied, wherein detecting the extent to which the target timing margin is satisfied or not satisfied comprises:
 after delaying the input signal in the first path by the first delay, consecutively delaying the input signal by a plurality of delay elements in a delay line; and 
 for each delay element in the delay line, producing an output signal corresponding to the signal state at the input of the delay element. 
 
 
     
     
       12. The method of  claim 11 , wherein comparing the input signal in the second path with the delayed input signal in the first path comprises performing a logic operation on the outputs from the first path and the second path. 
     
     
       13. The method of  claim 11 , wherein:
 if the input signal in the first path is delayed relative to the input signal in the second path by an amount of time less than a predetermined period of time plus the target timing margin, then the produced output indicates that the target timing margin has been satisfied, and 
 if the input signal in the first path is delayed relative to the input signal in the second path by an amount of time greater than the predetermined period of time plus the target timing margin, then the produced output indicates that the target timing margin has not been satisfied. 
 
     
     
       14. The method of  claim 11 , wherein detecting the extent to which the target timing margin is satisfied or not satisfied further comprises:
 performing, for each consecutive pair of output signals corresponding to a consecutive pair of delay elements in the delay line, a logical operation to determine, based on the consecutive pair of output signals, whether the input signal has reached a corresponding delay element in the delay line at a time determined by a clock signal; and 
 outputting a result of the logical operation corresponding to at least one consecutive pair of output signals. 
 
     
     
       15. The method of  claim 11 , wherein the first shift register comprises a first plurality of shift elements, and the second shift register comprises a second plurality of shift elements. 
     
     
       16. An apparatus for monitoring timing in a critical path in an integrated circuit, the critical path having a target timing margin, the apparatus comprising:
 (a) means for splitting an input signal into a first path including a first shift register and a second path including a second shift register; 
 (b) means for delaying the input signal in the first path by a first delay; 
 (c) means for comparing the input signal in the second path with the delayed input signal in the first path; 
 (d) means for producing, based on the comparison, an output indicating whether the target timing margin is satisfied or not satisfied; and 
 (e) means for detecting the extent to which the target timing margin is satisfied or not satisfied, the means for detecting comprising:
 means for consecutively delaying the input signal by a plurality of delay elements in a delay line, after delaying the input signal in the first path by the first delay; and 
 means for producing, for each delay element in the delay line, an output signal corresponding to the signal state at the input of the delay element. 
 
 
     
     
       17. An integrated circuit having a monitor circuit for monitoring timing in a critical path in the integrated circuit, the critical path having a target timing margin, the monitor circuit comprising:
 a first shift register having an input and an output, the first shift register including a delay circuit that applies a delay value to a received signal; 
 a second shift register having an input and an output, wherein the inputs of the first and second shift registers are connected together to form a signal input node capable of receiving an input signal; and 
 a logic circuit having an output and at least two inputs, each input connected to a corresponding one of the outputs of the first and second shift registers, wherein the output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied, wherein:
 the delay circuit comprises:
 a gross-delay element adapted to provide a gross delay value; and 
 a fine-delay detector circuit adapted to generate, based on the gross delay value, an output signal indicating the extent to which the target timing margin is satisfied.