Offset compensation scheme using a DAC

Abstract

An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

1. A circuit, comprising:
 one or more components that introduce an undesired current or voltage offset; and 
 a digital-to-analog converter (DAC) configured to inject current or voltage that at least in part compensates for the undesired current or voltage offset. 
 
     
     
       2. A circuit as recited in  claim 1 , wherein the current or voltage injected into the circuit by the DAC comprises a positive or negative polarity. 
     
     
       3. A circuit as recited in  claim 1 , wherein the injected current or voltage shifts a current or voltage of the circuit. 
     
     
       4. A circuit as recited in  claim 1 , wherein the injected current or voltage is similar in magnitude but opposite in polarity to the undesired current or voltage offset. 
     
     
       5. A circuit as recited in  claim 1 , wherein injecting current or voltage into the circuit comprises drawing current or voltage from the circuit. 
     
     
       6. A circuit as recited in  claim 1 , wherein the DAC has a variable gain. 
     
     
       7. A circuit as recited in  claim 1 , wherein a reference current or voltage associated with the DAC depends on a transconductance of a differential pair of the circuit. 
     
     
       8. A circuit as recited in  claim 1 , wherein range of the DAC is changed by scaling a reference current or voltage associated with the DAC. 
     
     
       9. A circuit as recited in  claim 1 , wherein a reference current or voltage associated with the DAC comprises a scaled version of a bandgap current or voltage. 
     
     
       10. A circuit as recited in  claim 1 , further comprising DAC bias circuitry. 
     
     
       11. A circuit as recited in  claim 10 , wherein the DAC bias circuitry comprises a transconductance replica circuit. 
     
     
       12. A circuit as recited in  claim 10 , wherein the DAC is a first DAC and further comprising a second DAC in the DAC bias circuitry for scaling a reference current or voltage associated with the first DAC. 
     
     
       13. A circuit as recited in  claim 1 , wherein a binary search algorithm is employed to calibrate the DAC. 
     
     
       14. A circuit as recited in  claim 1 , wherein a sequential search algorithm is employed to calibrate the DAC. 
     
     
       15. A circuit as recited in  claim 1 , wherein calibration of the DAC includes sweeping the DAC for one or more values of gain when the undesired current or voltage offset is applied and calibrating the DAC to a value associated with a transition boundary. 
     
     
       16. A circuit as recited in  claim 1 , wherein a reference current or voltage associated with the DAC is scaled based on a calibration value of the DAC. 
     
     
       17. A circuit as recited in  claim 1 , wherein calibration of the DAC is performed using an operating clock frequency of the circuit. 
     
     
       18. A circuit as recited in  claim 1 , wherein the DAC is implemented in NMOS (n-type metal-oxide-semiconductor field effect transistors). 
     
     
       19. A circuit as recited in  claim 18 , wherein the DAC is controlled by low voltage logic. 
     
     
       20. A circuit as recited in  claim 1 , wherein the circuit comprises an amplifier. 
     
     
       21. A circuit as recited in  claim 1 , wherein the circuit comprises a slice of an analog-to-digital converter (ADC). 
     
     
       22. A circuit as recited in  claim 1 , wherein the circuit comprises one slice of a plurality of slices included in an analog-to-digital converter (ADC) and wherein the DAC comprises one DAC of a DAC array associated with the ADC. 
     
     
       23. A circuit as recited in  claim 22 , wherein the plurality of DACs included in the DAC array of the ADC are calibrated sequentially, in parallel, or in groups. 
     
     
       24. A method, comprising:
 identifying an undesired current or voltage offset in a circuit; and 
 at least in part compensating for the undesired current or voltage offset using a digital-to-analog converter (DAC) that injects current or voltage into the circuit. 
 
     
     
       25. A method as recited in  claim 24 , wherein the current or voltage injected into the circuit by the DAC comprises a positive or negative polarity. 
     
     
       26. A method as recited in  claim 24 , wherein the injected current or voltage shifts a current or voltage of the circuit. 
     
     
       27. A method as recited in  claim 24 , wherein the injected current or voltage is similar in magnitude but opposite in polarity to the undesired current or voltage offset. 
     
     
       28. A method as recited in  claim 24 , wherein a range of the DAC is changed by scaling a reference current or voltage associated with the DAC. 
     
     
       29. A computer program product embodied in a non-transitory computer readable medium and comprising computer instructions which when executed cause a processor to:
 identify an undesired current or voltage offset in a circuit; and 
 at least in part compensate for the undesired current or voltage offset using a digital-to-analog converter (DAC) that injects current or voltage into the circuit. 
 
     
     
       30. A computer program product as recited in  claim 29 , wherein current or voltage injected into the circuit by the DAC comprises a positive or negative polarity.