Speech recognition circuit and method

Abstract

A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to the scores.

1. An accelerator for calculating distances for a speech recognition circuit, the accelerator comprising:
 a calculating circuit for calculating distances indicating the similarity between a feature vector and a plurality of predetermined acoustic states of an acoustic model, wherein the feature vector comprises a plurality of extracted and/or derived quantities from an audio signal during a defined audio time frame; 
 first and second storage circuits, each for storing calculated distances for at least one said audio time frame, and for making said stored distances available for use by another part of the speech recognition circuit; and 
 a control circuit for controlling read and write access to the first and second storage circuits, said control circuit being configured to allow writing to one said storage circuit while the other said storage circuit is available for reading, to allow first calculated distances for one audio time frame to be written to one said storage circuit while second calculated distances for an earlier audio time frame are made available for reading from the other said storage circuit. 
 
     
     
       2. The accelerator of  claim 1 , wherein the control circuit is configured to alternate which of the first and second storage circuits is available for reading, and which of the first and second storage circuits is available for writing, as each new feature vector is processed by the calculating circuit. 
     
     
       3. The accelerator of  claim 1 , wherein the control circuit is adapted to store the distance for each of a plurality of states. 
     
     
       4. The accelerator of  claim 1 , wherein the first and second storage circuits are interfaced to a processor in the speech recognition circuit as different memory locations within the processor's memory map. 
     
     
       5. The accelerator of  claim 1 , wherein the first and second storage circuits are interfaced to a processor in the speech recognition circuit as being mapped to a first fixed memory address when configured for reading and/or to a second fixed memory address when configured for writing. 
     
     
       6. The accelerator of  claim 1 , wherein the control circuit is adapted to release a result memory after a search stage has processed the contents, by informing the accelerator that it can overwrite the results in said memory. 
     
     
       7. The accelerator of  claim 1 , further comprising additional result memories, where at any time at most one result memory is configured for writing, and at least one result memory is configured for reading. 
     
     
       8. The accelerator of  claim 7 , wherein the results memories are configured for random access of the distance results in the result memories, as they are needed by the search stage. 
     
     
       9. The accelerator of  claim 7 , wherein the result memories are accessible in a round-robin fashion. 
     
     
       10. The accelerator of  claim 1 , wherein the said calculating circuit is configured to autonomously calculate distances for every acoustic state defined by the acoustic model. 
     
     
       11. A non-transitory storage medium storing processor implementable code for controlling at least one processor to calculate distances for speech recognition processing, the code comprising:
 code for controlling the processor to calculate distances indicating the similarity between a feature vector and a plurality of predetermined acoustic states of an acoustic model, wherein the feature vector comprises a plurality of extracted and/or derived quantities from an audio signal during a defined audio time frame; 
 code for controlling the processor to store, in each of a first and second memory, calculated distances for at least one said audio time frame, and for making said stored distances available for use by another part of the speech recognition process; and 
 code for controlling the processor to control read and write access to the first and second memories, to allow writing to one said memory while the other said memory is available for reading, to allow first calculated distances for one audio time frame to be written to one said memory while second calculated distances for an earlier audio time frame are made available for reading from the other said memory.