Method and system for generating an integrated circuit chip facility waveform from a series of chip snapshots

Abstract

Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

1. A method comprising:
 (a) selecting a set of state holding elements of an integrated circuit chip; 
 (b) configuring a clockstop request delay to an initial number of clock cycles; 
 (c) generating an error condition in said integrated circuit chip; 
 (d) generating a clockstop request in response to said error condition; 
 (e) delaying said clockstop request by a number of clock cycles equal to said clockstop request delay; 
 after (e), (f) reading out a state of each state holding element of said set of state holding elements; 
 after (f), (g) incrementing said clockstop request delay by a fixed number of clock cycles; and 
 after (g), (h) repeating steps (c) through (f) a predetermined number of times or until an instruction to stop. 
 
     
     
       2. The method of  claim 1 , further comprising:
 between (e) and (g), storing said state of each state holding element of set of state holding elements and a current value of said clockstop request delay as a snapshot; and 
 after (h), combining multiple snapshots having different clockstop request delays into a chip facility waveform. 
 
     
     
       3. The method of  claim 1 , wherein each time through (c) a same error condition is generated. 
     
     
       4. The method of  claim 1 , (c) further including:
 before said generating said error condition, configuring a trigger condition for said clockstop request. 
 
     
     
       5. The method of  claim 1 , wherein said error condition is generated by a trigger. 
     
     
       6. The method of  claim 1 , wherein said integrated circuit chip is a physical integrated circuit chip. 
     
     
       7. A test system including a computer comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed by the processor implement a method for generating a chip facility waveform, said method comprising the computer implemented steps of:
 (a) selecting a set of state holding elements of an integrated circuit chip; 
 (b) configuring a clockstop request delay to an initial number of clock cycles; 
 (c) generating an error condition in said integrated circuit chip; 
 (d) generating a clockstop request in response to said error condition; 
 (e) delaying said clockstop request by a number of clock cycles equal to said clockstop request delay; 
 after (e), (f) reading out a state of each state holding element of said set of state holding elements; 
 after (f), (g) incrementing said clockstop request delay by a fixed number of clock cycles; and 
 after (g), (h) repeating steps (c) through (f) a predetermined number of times or until an instruction to stop. 
 
     
     
       8. The test system of  claim 7 , the method further including the step of:
 between (e) and (g), storing said state of each state holding element of set of state holding elements and a current value of said clockstop request delay as a snapshot; and 
 after (h), combining multiple snapshots having different clockstop request delays into said chip facility waveform. 
 
     
     
       9. The test system of  claim 7 , wherein each time through method step (c) a same error condition is generated. 
     
     
       10. The test system of  claim 7 , method step (c) further including:
 before said generating said error condition, configuring a trigger condition for said clockstop request. 
 
     
     
       11. The test system of  claim 7 , wherein in said method, said error condition is generated by a trigger. 
     
     
       12. The test system of  claim 7 , wherein said integrated circuit chip is a physical integrated circuit chip. 
     
     
       13. A method comprising:
 (a) selecting a set of state holding elements of an integrated circuit chip; 
 (b) generating an error condition in said integrated circuit chip; 
 (c) generating and executing a clockstop request in response to said error condition; 
 after (c), (d) generating a snapshot of actual states of each of said state holding elements of said set of state holding elements; 
 (e) determining next previous states of each state holding element of said set of state holding elements based on respective states of each state holding element of said set of state holding element of a last generated snapshot and based on a description of circuit elements of said integrated circuit chip and interconnections between said circuit elements; 
 after (e), (f) generating a snapshot of said next previous states of each state holding element of said set of state holding elements; and 
 after (f), (g) repeating steps (e) and (f) a predetermined number of times or until an instruction to stop. 
 
     
     
       14. The method of  claim 13 , further comprising:
 storing all snapshots and respective clock cycles of said snapshots. 
 
     
     
       15. The method of  claim 13 , further comprising:
 after (g), combining multiple snapshots into a chip facility waveform in a sequential clock cycle order. 
 
     
     
       16. The method of  claim 13 , (e) further including:
 determining said next previous states of each state holding element of said set of state holding elements using a simulator running a computer model of said integrated circuit. 
 
     
     
       17. The method of  claim 16 , wherein said model is generated from a netlist and input to said model is states of each state holding element of said set of state holding elements from a last generated snapshot. 
     
     
       18. The method of  claim 13 , wherein said integrated circuit chip is a physical integrated circuit chip. 
     
     
       19. A test system including a computer comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed by the processor implement a method for generating a chip facility waveform, said method comprising the computer implemented steps of:
 (a) selecting a set of state holding elements of an integrated circuit chip; 
 (b) generating an error condition in said integrated circuit chip; 
 (c) generating and executing a clockstop request in response to said error condition; 
 after (c), (d) generating a snapshot of actual states of each of said state holding elements of said set of state holding elements; 
 (e) determining next previous states of each state holding element of said set of state holding elements based on respective states of each state holding element of said set of state holding element of a last generated snapshot and based on a description of circuit elements of said integrated circuit chip and interconnections between said circuit elements; 
 after (e), (f) generating a snapshot of said next previous states of each state holding element of said set of state holding elements; and 
 after (f), (g) repeating steps (e) and (f) a predetermined number of times or until an instruction to stop. 
 
     
     
       20. The test system of  claim 19 , the method further comprising:
 storing all snapshots and respective clock cycles of said snapshots. 
 
     
     
       21. The test system of  claim 19 , the method further comprising:
 after (f), combining multiple snapshots into a chip facility waveform in a sequential clock cycle order. 
 
     
     
       22. The test system of  claim 19 , method step (e) further including:
 determining said next previous states of each state holding element of said set of state holding elements using a simulator running a computer model of said integrated circuit. 
 
     
     
       23. The test system of  claim 22 , wherein said model is generated from a netlist and input to said model is states of each state holding element of said set of state holding elements from a last generated snapshot. 
     
     
       24. The test system of  claim 19 , wherein said integrated circuit chip is a physical integrated circuit chip.