Stacked memory module and system

Abstract

A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

1. A three dimensional memory system comprising:
 a master chip; 
 at least one slave chip stacked with the master chip; 
 through electrodes formed through the at least one slave chip; 
 an external data bus that is bidirectional or unidirectional; and 
 a master internal data bus that is bidirectional when one rank is formed in the stacked chips and that includes unidirectional read and write buses when a plurality of ranks are formed in the stacked chips, when the external data bus is bidirectional. 
 
     
     
       2. The three dimensional memory system of  claim 1 , wherein the master internal data bus includes unidirectional read and write buses for any number of ranks formed in the stacked chips when the external data bus is unidirectional. 
     
     
       3. The three dimensional memory system of  claim 1 , wherein the master internal data bus includes a respective separate data bus formed for each bank group when a plurality of bank groups are formed in the stacked chips. 
     
     
       4. The three dimensional memory system of  claim 1 , further comprising:
 a slave internal data bus that is bidirectional when the external data bus is either bidirectional or unidirectional. 
 
     
     
       5. The three dimensional memory system of  claim 1 , further comprising:
 a slave internal data bus that is bidirectional when one rank or a plurality of ranks are formed in the stacked chips. 
 
     
     
       6. The three dimensional memory system of  claim 1 , further comprising:
 a slave internal data bus that is bidirectional when one bank group or a plurality of bank groups are formed in the stacked chips.