Solid state imaging apparatus, method for driving the same and camera using the same

Abstract

A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.

1. A solid state imaging apparatus comprising:
 a plurality of photodiodes arranged in an array; 
 a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; 
 a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; 
 a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; 
 a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; 
 a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, 
 wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, 
 the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, 
 the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, 
 the first read-out line is adjacent to the second read-out line, 
 the second read-out line is disposed between the first read-out line and the third read-out line, 
 the third read-out line is disposed between the second read-out line and the fourth read-out line, 
 the first read-out line is connected to the first photodiode in row m via the first transfer transistor, where m is a positive integer, 
 the second read-out line is connected to the second photodiode in the row m via the second transfer transistor, 
 the third read-out line is connected to the third photodiode in row m+1 via the third transfer transistor, 
 the fourth read-out line is connected to the fourth photodiode in the row m+1 via the fourth transfer transistors, 
 the first photodiode and the third photodiode are disposed in one of column n and column n+1, where n is a positive integer, 
 the second photodiode and the fourth photodiode are disposed in the other of the column n and the column n+1, and 
 one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. 
 
     
     
       2. The solid state imaging apparatus of  claim 1 , wherein the row m is adjacent to the row m+1, and
 the column n is adjacent to the column n+1. 
 
     
     
       3. The solid state imaging apparatus of  claim 1 , wherein no read-out line is disposed between the second read-out line and the third read-out line, and
 no read-out line is disposed between the third read-out line and the fourth read-out line. 
 
     
     
       4. The solid state imaging apparatus of  claim 1 , wherein one of the plurality of floating diffusion sections is connected to the first photodiode via the first transfer transistor,
 the one of the plurality of floating diffusion sections is connected to the second photodiode via the second transfer transistor, 
 the one of the plurality of floating diffusion sections is connected to the third photodiode via the third transfer transistor, and 
 the one of the plurality of floating diffusion sections is connected to the fourth photodiode via the fourth transfer transistor. 
 
     
     
       5. The solid state imaging apparatus of  claim 1 , wherein one of the plurality of floating diffusion sections is disposed between the column n and the column n+1. 
     
     
       6. The solid state imaging apparatus of  claim 1 , wherein one of the plurality of pixel amplifier transistors is disposed between the row m and the row m+1. 
     
     
       7. The solid state imaging apparatus of  claim 1 , wherein one of the plurality of floating diffusion sections is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       8. The solid state imaging apparatus of  claim 1 , wherein the plurality of read-out lines and one of the plurality of signal lines intersect with each other. 
     
     
       9. The solid state imaging apparatus of  claim 1 , further comprising a plurality of row select transistors each being connected to one of the plurality of pixel amplifier transistors. 
     
     
       10. The solid state imaging apparatus of  claim 9 , wherein one of the plurality of row select transistors is disposed between the row m and the row m+1. 
     
     
       11. The solid state imaging apparatus of  claim 9 , wherein one of the plurality of row select transistors is disposed between one of the plurality of pixel amplifier transistors and one of the plurality of signal lines. 
     
     
       12. The solid state imaging apparatus of  claim 9 , wherein one of the plurality of row select transistors is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       13. The solid state imaging apparatus of  claim 9 , wherein one of the plurality of row select transistors is adjacent to one of the plurality of pixel amplifier transistors. 
     
     
       14. The solid state imaging apparatus of  claim 1 , further comprising a plurality of VDDCELL lines each being connected to one of the plurality of the reset transistors,
 wherein one of the column n and the column n+1 is disposed between one of the plurality of VDDCELL lines and the other of the column n and the column n+1. 
 
     
     
       15. A solid state imaging apparatus comprising:
 a plurality of photodiodes arranged in an array; 
 a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; 
 a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; 
 a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; 
 a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; 
 a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, 
 wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, 
 the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, 
 the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, 
 the first photodiode is in row m and column n, where m and n are a positive integer respectively, 
 the second photodiode is in row m and column n+1, 
 the third photodiode is in row m+1 and column n, 
 the fourth photodiode is in row m+1 and column n+1, 
 the first read-out line is adjacent to the second read-out line, 
 the second read-out line is disposed between the first read-out line and the third read-out line, 
 the third read-out line is disposed between the second read-out line and the fourth read-out line, 
 the first read-out line is connected to the second photodiode via the first transfer transistor, 
 the second read-out line is connected to the first photodiode via the second transfer transistor, 
 the third read-out line is connected to the fourth photodiode via the third transfer transistor, 
 the fourth read-out line is connected to the third photodiode via the fourth transfer transistor, and 
 one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. 
 
     
     
       16. The solid state imaging apparatus of  claim 15 , wherein the row m is adjacent to the row m+1, and
 the column n is adjacent to the column n+1. 
 
     
     
       17. The solid state imaging apparatus of  claim 15 , wherein no read-out line is disposed between the second read-out line and the third read-out line, and
 no read-out line is disposed between the third read-out line and the fourth read-out line. 
 
     
     
       18. The solid state imaging apparatus of  claim 15 , wherein one of the plurality of floating diffusion sections is connected to the first photodiode via the second transfer transistor,
 the one of the plurality of floating diffusion sections is connected to the second photodiode via the first transfer transistor, 
 the one of the plurality of floating diffusion sections is connected to the third photodiode via the fourth transfer transistor, and 
 the one of the plurality of floating diffusion sections is connected to the fourth photodiode via the third transfer transistor. 
 
     
     
       19. The solid state imaging apparatus of  claim 15 , wherein one of the plurality of floating diffusion sections is disposed between the column n and the column n+1. 
     
     
       20. The solid state imaging apparatus of  claim 15 , wherein one of the plurality of pixel amplifier transistors is disposed between the row m and the row m+1. 
     
     
       21. The solid state imaging apparatus of  claim 15 , wherein one of the plurality of floating diffusion sections is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       22. The solid state imaging apparatus of  claim 15 , wherein the plurality of read-out lines and one of the plurality of signal lines intersect with each other. 
     
     
       23. The solid state imaging apparatus of  claim 15 , further comprising a plurality of row select transistors each being connected to one of the plurality of pixel amplifier transistors. 
     
     
       24. The solid state imaging apparatus of  claim 23 , wherein one of the plurality of row select transistors is disposed between the row m and the row m+1. 
     
     
       25. The solid state imaging apparatus of  claim 23 , wherein one of the plurality of row select transistors is disposed between one of the plurality of pixel amplifier transistors and one of the plurality of signal lines. 
     
     
       26. The solid state imaging apparatus of  claim 23 , wherein one of the plurality of row select transistors is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       27. The solid state imaging apparatus of  claim 23 , wherein one of the plurality of row select transistors is adjacent to one of the plurality of pixel amplifier transistors. 
     
     
       28. The solid state imaging apparatus of  claim 15 , further comprising a plurality of VDDCELL lines each being connected to one of the plurality of the reset transistors,
 wherein one of the column n and the column n+1 is disposed between one of the plurality of VDDCELL lines and the other of the column n and the column n+1. 
 
     
     
       29. A solid state imaging apparatus comprising:
 a plurality of photodiodes arranged in an array; 
 a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; 
 a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; 
 a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; 
 a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; 
 a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, 
 wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, 
 the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, 
 the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, 
 the first photodiode is in row m and column n, where m and n are a positive integer respectively, 
 the second photodiode is in row m and column n+1, 
 the third photodiode is in row m+1 and column n, 
 the fourth photodiode is in row m+1 and column n+1, 
 the first read-out line is adjacent to the second read-out line, 
 the second read-out line is disposed between the first read-out line and the third read-out line, 
 the third read-out line is disposed between the second read-out line and the fourth read-out line, 
 the first read-out line is connected to the first photodiode via the first transfer transistor, 
 the second read-out line is connected to the second photodiode via the second transfer transistor, 
 the third read-out line is connected to the third photodiode via the third transfer transistor, 
 the fourth read-out line is connected to the fourth photodiode via the fourth transfer transistor, and 
 one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. 
 
     
     
       30. The solid state imaging apparatus of claim of  claim 29 , wherein the row m is adjacent to the row m+1, and
 the column n is adjacent to the column n+1. 
 
     
     
       31. The solid state imaging apparatus of  claim 29 , wherein no read-out line is disposed between the second read-out line and the third read-out line, and
 no read-out line is disposed between the 
 
       third read-out line and the fourth read-out line. 
     
     
       32. The solid state imaging apparatus of  claim 29 , wherein one of the plurality of floating diffusion sections is connected to the first photodiode via the first transfer transistor,
 the one of the plurality of floating diffusion sections is connected to the second photodiode via the second transfer transistor, 
 the one of the plurality of floating diffusion sections is connected to the third photodiode via the third transfer transistor, and 
 the one of the plurality of floating diffusion sections is connected to the fourth photodiode via the fourth transfer transistor. 
 
     
     
       33. The solid state imaging apparatus of  claim 29 , wherein one of the plurality of floating diffusion sections is disposed between the column n and the column n+1. 
     
     
       34. The solid state imaging apparatus of  claim 29 , wherein one of the plurality of pixel amplifier transistors is disposed between the row m and the row m+1. 
     
     
       35. The solid state imaging apparatus of  claim 29 , wherein one of the plurality of floating diffusion sections is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       36. The solid state imaging apparatus of  claim 29 , wherein the plurality of read-out lines and one of the plurality of signal lines intersect with each other. 
     
     
       37. The solid state imaging apparatus of  claim 29 , further comprising a plurality of row select transistors each being connected to one of the plurality of pixel amplifier transistors. 
     
     
       38. The solid state imaging apparatus of  claim 37 , wherein one of the plurality of row select transistors is disposed between the row m and the row m+1. 
     
     
       39. The solid state imaging apparatus of  claim 37 , wherein one of the plurality of row select transistors is disposed between one of the plurality of pixel amplifier transistors and one of the plurality of signal lines. 
     
     
       40. The solid state imaging apparatus of  claim 37 , wherein one of the plurality of row select transistors is disposed between one of the plurality of reset transistors and one of the plurality of signal lines. 
     
     
       41. The solid state imaging apparatus of  claim 37 , wherein one of the plurality of row select transistors is adjacent to one of the plurality of pixel amplifier transistors. 
     
     
       42. The solid state imaging apparatus of  claim 29 , further comprising a plurality of VDDCELL lines each being connected to one of the plurality of the reset transistors,
 wherein one of the column n and the column n+1 is disposed between one of the plurality of VDDCELL lines and the other of the column n and the column n+1.