High-voltage switch using three FETs

Abstract

Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

1. A switch circuit for providing a differentially switched high-voltage signal by switching a high supply voltage in response to at least one logic-level control signal, comprising:
 a first pair of differentially coupled chains, each having at least three serially coupled field effect transistors (FETs), the first chains receiving the high supply voltage and switching to selectively couple the high supply voltage to a first differential output voltage node or a second differential output voltage node output for outputting the differential high-voltage output signal; and 
 a control/bias circuit including a second pair of differentially coupled chains, each of the chain in the second pair having at least two serially coupled FETs and receiving an intermediate supply voltage for providing bias voltages to at least one of the FETs of each chain in the first pair. 
 
     
     
       2. The circuit of  claim 1 , in which the first chains include:
 a first and a second pFETs, each having a source, a drain, a gate, and a well, the source and the well of both pFETs coupled to receive the high supply voltage, the drain of the first pFET coupled to a first intermediate node and its gate coupled to a second intermediate node, the drain of the second pFET coupled to the second intermediate node and its gate coupled to the first intermediate node, 
 a third and a fourth pFETs, each having a source, a drain, a gate, and a well, the source and the well of the third pFET coupled to the first intermediate node, the gate of the third pFET coupled to receive a first intermediate supply voltage signal from the control/bias circuit of a voltage level is lower than the high supply voltage, the source and the well of the fourth pFET coupled to the second intermediate node, and the gate of the fourth pFET coupled to receive a second intermediate supply voltage signal from the control/bias circuit of a voltage level lower than the high supply voltage, and 
 a fifth and a sixth pFET, each having a source, a drain, and a well, the source and the well of the fifth pFET coupled to the drain of the third pFET, the drain of the fifth pFET coupled to the first differential output voltage node for providing a first component of the differential high-voltage signal, the source and the well of the sixth pFET coupled to the drain of the fourth pFET, the drain of the sixth pFET coupled to the second differential output voltage node for providing a second component of the differential high-voltage signal. 
 
     
     
       3. The circuit of  claim 2 , in which:
 the fifth pFET also includes a gate that is coupled to a first node of the control/bias circuit, the first node providing the first bias voltage that is substantially equal to the voltage level of the first intermediate supply voltage when the control signal is true, and for providing a second bias voltage of a voltage level lower than the first intermediate supply voltage when the control signal is false, and 
 the sixth pFET also includes a gate that is coupled to a second node of the control/bias circuit, the second node providing a third bias voltage that is substantially equal to the voltage level of the second intermediate supply voltage when the control signal is false, and for providing a fourth bias voltage of a voltage level lower than the first intermediate supply voltage when the control signal is true. 
 
     
     
       4. The circuit of  claim 3 , in which the control/bias circuit further includes a circuit portion adapted to reset one of the first and a second intermediate nodes to ground or logical false signal, while allowing a non-reset intermediate node to follow the high supply voltage. 
     
     
       5. The circuit of  claim 3 , in which the control/bias circuit further includes
 a first diode having a cathode coupled to the source of the third pFET, and an anode coupled to the gate of the third pFET, and 
 a second diode having a cathode coupled to the source of the fourth pFET, and an anode coupled to the gate of the fourth pFET. 
 
     
     
       6. The circuit of  claim 5 , in which the first and second diodes are pFETs configured as diodes, each pFET configured as a diode having its source coupled to its gate to form an anode, the drain becoming a cathode. 
     
     
       7. The circuit of  claim 3 , in which values of the first intermediate and alternative first intermediate supply voltages are approximately two thirds of a value of the high supply voltage. 
     
     
       8. The circuit of  claim 3 , in which values of the first intermediate and alternative first intermediate supply voltages are between five sixths and one-half of a value of the high supply voltage. 
     
     
       9. The circuit of  claim 3 , in which a value of the second intermediate supply voltage is approximately one third of a value of the high supply voltage. 
     
     
       10. The circuit of  claim 3 , in which a value of the second intermediate supply voltage is between one half and one sixth of a value of the high supply voltage. 
     
     
       11. The circuit of  claim 1 , wherein the pull-down block comprises:
 a first portion coupling the first differential output voltage node to a VCOM voltage source, and 
 a second portion coupling the second differential output voltage node to the VCOM voltage source. 
 
     
     
       12. The circuit of  claim 11 , in which a value of the VCOM voltage source is less than 6 V. 
     
     
       13. The circuit of  claim 11 , in which
 a first nFET that has its drain coupled to receive the first component of the differentially switched high-voltage signal, its gate coupled to receive a third intermediate supply voltage, its source coupled to the VCOM voltage source through a third nFET responsive to the control signal, and 
 a second nFET that has its drain coupled to receive the second component of the differentially switched high-voltage signal, its gate coupled to receive the third intermediate supply voltage, its source coupled to the VCOM voltage source through a fourth nFET responsive to a complement of the control signal. 
 
     
     
       14. The circuit of  claim 13 , in which
 a fifth nFET has its source coupled to receive the third intermediate supply voltage, its gate and its drain coupled to a drain of the third nFET to receive complement of the control signal, and 
 a sixth nFET has its source coupled to receive the third intermediate supply voltage, its gate and its drain coupled to a drain of the fourth nFET to receive the control signal. 
 
     
     
       15. The circuit of  claim 13 , in which a value of the third intermediate supply voltage that is sufficient to turn on one of the first and second nFETs. 
     
     
       16. The circuit of  claim 13 , in which each of the first and the second nFETs includes a drain having an n+ region disposed in a first n-well. 
     
     
       17. The circuit of  claim 16 , in which the high supply voltage is switched in response to at least two additional control signals. 
     
     
       18. The circuit of  claim 16 , in which the circuit is reset in response to a second control signal prior to assuming regular operation. 
     
     
       19. The circuit of  claim 16 , in which the circuit is preset in response to a third control signal prior to assuming regular operation. 
     
     
       20. The circuit of  claim 1 , in which the second chains include a first and a second pFET, each having a source, a drain, a gate, and a well, the source and the well of the first pFET coupled to the intermediate voltage supply, the gate of the first pFET coupled to the drain of the second pFET, the drain of the first pFET coupled to a first node of the second chains for providing a first component of the bias voltages, the source and the well of the second pFET coupled to a first intermediate voltage supply, the gate of the second pFET coupled to the drain of the first pFET, the drain of the first pFET coupled to a second node of the second chains for providing a second component of the bias voltages.