Level shifters and integrated circuits thereof

Abstract

An integrated circuit includes a level shifter configured to receive a first voltage signal that swings between a first voltage level and a second voltage level, outputting a second voltage signal that swings between the first voltage level and a third voltage level. The third voltage level is higher than the second voltage level. An inverter is coupled with the level shifter. The inverter can receive the second voltage, outputting a third voltage signal that swings between the third voltage level and a fourth voltage level. The fourth voltage level is lower than the third voltage level and higher than the first voltage level.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a level shifter configured to receive a first voltage signal that swings between a first voltage level and a second voltage level and output a second voltage signal that swings between the first voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level; and 
 an inverter coupled with the level shifter, the inverter being configured to receive the second voltage signal and output a third voltage signal that swings between the third voltage level and a fourth voltage level, wherein the fourth voltage level is lower than the third voltage level and higher than the first voltage level, 
 wherein the level shifter comprises a first transistor of a first type coupled between a first power supply node and an output node of the level shifter, the first power supply node is coupled with the third voltage level, and a gate of the first transistor of the first type is configured to receive a fourth voltage signal that swings between the third voltage level and the fourth voltage level. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the first transistor of the first type is a first high voltage (HV) device. 
     
     
       3. The integrated circuit of  claim 1 , wherein a voltage drop between a source and a gate of the first transistor of the first type is no more than a difference between the third voltage level and the fourth voltage level. 
     
     
       4. The integrated circuit of  claim 1 , wherein the level shifter further comprises:
 a second transistor of the first type coupled with the output node of the level shifter; and 
 a third transistor of the first type coupled with the second transistor of the first type, wherein a gate of the third transistor of the first type is coupled with the output node of the level shifter. 
 
     
     
       5. The integrated circuit of  claim 4 , wherein the level shifter further comprises at least one first transistor of a second type coupled with the output node of the level shifter and the at least one first transistor of the second type includes a second high voltage (HV) device. 
     
     
       6. The integrated circuit of  claim 1 , wherein the inverter comprises a fourth transistor of the first type coupled between a second power supply node and an output node of the inverter, the second power supply node is coupled with the third voltage level, and a gate of the fourth transistor of the first type is configured to receive a fifth voltage signal that swings between the third voltage level and the fourth voltage level. 
     
     
       7. The integrated circuit of  claim 6 , wherein a voltage drop between a source and a gate of the fourth transistor of the first type is no more than a difference between the third voltage level and the fourth voltage level. 
     
     
       8. The integrated circuit of  claim 6 , wherein the inverter further comprises:
 a fifth transistor of the first type coupled between an input node of the inverter and the output node of the inverter; and 
 a sixth transistor of the first type coupled with the fifth transistor of the first type, wherein a gate of the sixth transistor of the first type is coupled with the input node of the level shifter. 
 
     
     
       9. The integrated circuit of  claim 8 , wherein the inverter further comprises at least one second transistor of the second type coupled with the output node of the inverter. 
     
     
       10. An integrated circuit comprising:
 a level shifter comprising:
 a first transistor of a first type coupled between a first power supply node and a first output node of the level shifter; 
 at least one first transistor of a second type coupled with the first output node of the level shifter; 
 a second transistor of the first type having a source and a drain, one of the source and the drain of the second transistor of the first type coupled with the first output node of the level shifter; and 
 a third transistor of the first type having a direct electrical connection with the other one of the source and the drain of the second transistor of the first type, wherein a gate of the third transistor of the first type is coupled with the first output node of the level shifter; and 
 
 an inverter coupled with the level shifter. 
 
     
     
       11. The integrated circuit of  claim 10 , wherein the first transistor of the first type is a first HV device and the at least one first transistor of a second type includes a second HV device. 
     
     
       12. The integrated circuit of  claim 10 , wherein the inverter comprises:
 a fourth transistor of the first type coupled between a second power supply node and an output node of the inverter; 
 a fifth transistor of the first type coupled between an input node of the inverter and a gate of the fourth transistor of the first type; 
 a sixth transistor of the first type coupled with the fifth transistor of the first type, wherein a gate of the sixth transistor of the first type is coupled with the input node of the inverter; and 
 at least one second transistor of the second type coupled with the output node of the inverter. 
 
     
     
       13. The integrated circuit of  claim 10 , wherein the level shifter further comprises:
 a seventh transistor of the first type coupled between a third power supply node and a second output node of the level shifter; 
 at least one third transistor of the second type coupled with the second output node of the level shifter; 
 an eighth transistor of the first type coupled with the second output node of the level shifter; and 
 a ninth transistor of the first type coupled with the eighth transistor of the first type, wherein a gate of the ninth transistor of the first type is coupled with the second output node of the level shifter. 
 
     
     
       14. A level shifter comprising:
 at least one input node configured to receive a first voltage signal that swings between a first voltage level and a second voltage level; 
 at least one output node configured to output a second voltage signal corresponding to the first voltage signal, the second voltage signal swinging between the first voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level; and 
 at least one first transistor of a first type coupled between the at least one input node and the at least one output node, wherein a gate of the at least one first transistor of the first type is capable of receiving a third voltage signal that swings between the third voltage level and a fourth voltage level and the fourth voltage level is higher than the first voltage level and lower than the third voltage level. 
 
     
     
       15. The level shifter of  claim 14 , wherein the at least one first transistor of the first type includes a first high voltage (HV) device. 
     
     
       16. The level shifter of  claim 14 , wherein a voltage drop between a source and a gate of the at least one first transistor of the first type is no more than a difference between the third voltage level and the fourth voltage level. 
     
     
       17. The level shifter of  claim 14  further comprises:
 at least one first transistor of a second type coupled with the at least one output node of the level shifter; 
 at least one second transistor of the first type coupled with the at least one output node of the level shifter; and 
 at least one third transistor of the first type coupled with the at least one second transistor of the first type, wherein a gate of the at least one third transistor of the first type is coupled with the at least one output node of the level shifter. 
 
     
     
       18. The level shifter of  claim 17 , wherein the least one first transistor of the second type includes a second high voltage (HV) device. 
     
     
       19. The integrated circuit of  claim 10 , wherein the third transistor of the first type has a source and a drain, one of the source and the drain of the third transistor of the first type is connected with the other one of the source and the drain of the second transistor of the first type.