Metal control gate formation in non-volatile storage

Abstract

Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.

What is claimed is: 
     
       1. A method of forming a memory array comprising non-volatile storage elements and transistors, the method comprising:
 forming a first region of polysilicon for floating gates of non-volatile storage elements and for lower portions of control gates of transistors; 
 forming a dielectric conformably over the first region of polysilicon to be used for an inter-poly dielectric of the non-volatile storage elements; 
 forming a second region of polysilicon conformably over the dielectric, the second region of polysilicon for lower portions of control gates of the non-volatile storage elements; 
 etching through the second region of polysilicon and the dielectric in regions in which the control gates of the transistors are to be formed to expose the first region of polysilicon; 
 depositing sacrificial material over at least the second region of polysilicon and the exposed portion of the first region of polysilicon; 
 forming first stacks for non-volatile storage elements from portions of the first region of polysilicon, portions of the dielectric, portions of the second region of polysilicon, and portions of the sacrificial material; 
 forming second stacks for control gates of transistors from portions of the first region of polysilicon and portions of the sacrificial material; 
 forming one or more insulating regions adjacent to the first stacks and the second stacks; 
 removing the sacrificial material to reveal first openings in the first stacks and second opening in the second stacks between the one or more insulating regions; and 
 depositing metal in the first openings and the second openings, control gates of the non-volatile storage elements are formed at least in part from the metal in the first openings and adjacent portions the second region of polysilicon, control gates of the transistors are formed at least in part from the metal in the second openings and adjacent portions of first region of polysilicon. 
 
     
     
       2. The method of  claim 1 , further comprising depositing a barrier layer at least over the exposed first region of polysilicon after etching through the second region of polysilicon and the dielectric and prior to forming metal in the first openings and the second openings. 
     
     
       3. The method of  claim 2 , wherein the barrier layer includes a material that prevents silicidation of the first region of polysilicon. 
     
     
       4. The method of  claim 3 , wherein the barrier layer includes one or more of titanium nitride, tungsten nitride, and hafnium nitride. 
     
     
       5. The method of  claim 1 , wherein the etching through the second region of polysilicon and the dielectric exposes portions of the dielectric, and further comprising depositing a protective layer of polysilicon at least over the exposed dielectric prior to depositing the sacrificial material. 
     
     
       6. The method of  claim 5 , wherein the dielectric and the sacrificial material each include nitride. 
     
     
       7. The method of  claim 1 , wherein the etching the second region of polysilicon and the dielectric creates cutout regions where control gates of the transistors are to be formed, the cutout regions expose portions of the dielectric, and further comprising depositing a protective layer of polysilicon at least over the exposed dielectric in the cutout regions prior to depositing the sacrificial material in the cutout regions. 
     
     
       8. The method of  claim 1 , wherein the etching the second region of polysilicon and the dielectric creates cutout regions where control gates of the transistors are to be formed, the cutout regions expose portions of the dielectric, and further comprising depositing a protective layer over the exposed dielectric in the cutout regions prior to depositing the sacrificial material in the cutout regions, the protective layer has a high etch selectivity with respect to the sacrificial material. 
     
     
       9. The method of  claim 8 , wherein at least some of the protective layer remains over the dielectric in the cutout regions after removing the sacrificial material. 
     
     
       10. The method of  claim 1 , wherein the sacrificial material includes one or more of SiN or amorphous carbon. 
     
     
       11. A method of forming a NAND string comprising non-volatile storage elements and select gate transistors, the method comprising:
 forming a first layer of polysilicon; 
 forming a dielectric over the first layer of polysilicon; 
 forming a second layer of polysilicon over the dielectric; 
 etching through the second layer of polysilicon and the dielectric in regions in which control gates of the select gate transistors are to be formed to expose the first layer of polysilicon; 
 depositing sacrificial material over the second layer of polysilicon and the exposed portion of the first layer of polysilicon; 
 forming first stacks for non-volatile storage elements from portions of the first layer of polysilicon, portions of the dielectric, portions of the second layer of polysilicon, and portions of the sacrificial material; 
 forming second stacks for control gates of the select gate transistors from portions of the first layer of polysilicon and portions of the sacrificial material; 
 forming insulation in openings between the first stacks and the second stacks; 
 removing the sacrificial material to reveal first openings in the first stacks and second opening in the second stacks between the insulation; and 
 depositing metal in the first openings and the second openings, control gates of the non-volatile storage elements are formed at least in part from the metal in the first openings and adjacent portions the second layer of polysilicon, control gates of the transistors are formed at least in part from the metal in the second openings and adjacent portions of first layer of polysilicon. 
 
     
     
       12. The method of  claim 11 , further comprising depositing a barrier layer over the exposed first layer of polysilicon after etching through the second layer of polysilicon and the dielectric and prior to forming metal in the first openings and the second openings. 
     
     
       13. The method of  claim 12 , wherein the barrier layer includes a material that prevents silicidation of the first layer of polysilicon. 
     
     
       14. The method of  claim 11 , wherein the etching the second layer of polysilicon and the dielectric creates cutout regions where control gates of the select gate transistors are to be formed, the cutout regions expose portions of the dielectric, and further comprising depositing a protective layer of polysilicon at least over the exposed dielectric in the cutout regions prior to depositing the sacrificial material in the cutout regions. 
     
     
       15. The method of  claim 14 , wherein at least some of the protective layer of polysilicon remains over the dielectric in the cutout regions after removing the sacrificial material. 
     
     
       16. The method of  claim 11 , wherein the sacrificial material includes one or more of SiN or amorphous carbon. 
     
     
       17. The method of  claim 11 , wherein the dielectric and the sacrificial material each include nitride.