Semiconductor device and method of manufacturing same

Abstract

There are provided: a silicon pillar that is formed almost perpendicularly to a main surface of a substrate; first and second impurity diffused layers that are arranged in a lower part and an upper part of the silicon pillar, respectively; a gate electrode that is arranged horizontally through the silicon pillar; and a gate insulating film that is arranged between the gate electrode and the silicon pillar. The silicon pillar consequently has a small volume, which makes it possible to reduce the leak current of the transistor or thyristor formed in the silicon pillar.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate; a plurality of first wirings each extending in a first direction; a plurality of second wirings each extending in a second direction perpendicular to the first direction; a plurality of first impurity diffusion layers; a plurality of silicon pillars; and a plurality of transistors arranged at intersections of the first wirings and the second wirings in a matrix configuration, wherein each of the transistors includes one of the silicon pillars projecting perpendicularly from a main surface of the semiconductor substrate; one of the first impurity diffusion layers formed in a lower part of the silicon pillar; and a second impurity diffusion layer formed in an upper part of the silicon pillar, a central part of the silicon pillar is divided into a first divided portion and a second divided portion, the lower part of the silicon pillar being connected with both of the first and second divided portions, the upper part of the silicon pillar being connected with both of the first and second divided portions, each of the first impurity diffusion layers diffuses into the semiconductor substrate so as to be continuous between the silicon pillars adjoining in the first direction, each of the first wirings being constituted by the first impurity diffusion layers continuous in the first direction, and each of the second wirings is arranged between the first and second divided portions of the corresponding transistors. 
     
     
       2. The semiconductor device as claimed in  claim 1 , wherein
 each of the transistors further includes a gate insulating film formed between the corresponding second wiring and each of the corresponding first and second divided portions, the corresponding second wiring constituting a gate electrode common to the corresponding first and second divided portions. 
 
     
     
       3. The semiconductor device as claimed in  claim 2 , wherein
 in case one of the second wirings is activated, channels electrically connecting the corresponding first and second impurity diffusion layers are formed in the corresponding first and second divided portions. 
 
     
     
       4. The semiconductor device as claimed in  claim 1 , wherein
 each of the transistors further includes an upper insulating film being arranged between a bottom surface of the corresponding second wiring and a top surface of the corresponding first impurity diffusion layer, and 
 a lower insulating film being arranged between a top surface of each of the corresponding second wiring and a bottom surface of the corresponding second impurity diffusion layer. 
 
     
     
       5. The semiconductor device as claimed in  claim 1 , further comprising capacitors being provided for each of the transistors, wherein
 each of the capacitors has an electrode electrically connected to the corresponding second impurity diffusion layer. 
 
     
     
       6. The semiconductor device as claimed in  claim 5 , wherein each of the first wirings is a bit line, and each of the second wirings is a word line. 
     
     
       7. A semiconductor device comprising: a semiconductor substrate; a plurality of first wirings each extending in a first direction; a plurality of second wirings each extending in a second direction perpendicular to the first direction; a plurality of first impurity diffusion layers; a plurality of silicon pillars; and a plurality of transistors arranged at intersections of the first wirings and the second wirings in a matrix configuration, wherein each of the transistors includes one of the silicon pillars projecting perpendicularly from a main surface of the semiconductor substrate; one of the first impurity diffusion layers formed in a lower part of the silicon pillar; and a second impurity diffusion layer formed in an upper part of the silicon pillar, a central part of the silicon pillar is divided into a first divided portion and a second divided portion, the lower part of the silicon pillar being connected with both of the first and second divided portions, the upper part of the silicon pillar being connected with both of the first and second divided portions, each of the first impurity diffusion layers diffuses into the semiconductor substrate so as to be continuous between the silicon pillars adjoining in the first direction, each of the first wirings being constituted by the first impurity diffusion layers continuous in the first direction, each of the second wirings is arranged between the first and second divided portions of the corresponding transistors, and the second wirings are not provided between the silicon pillars adjoining each other in the first direction. 
     
     
       8. The semiconductor device as claimed in  claim 7 , wherein the second impurity diffusion layers adjoining each other in the first direction are separated by an insulating film. 
     
     
       9. The semiconductor device as claimed in  claim 7 , wherein
 each of the transistors further includes a gate insulating film formed between the corresponding second wiring and each of the corresponding first and second divided portions, the corresponding second wiring constituting a gate electrode common to the corresponding first and second divided portions. 
 
     
     
       10. The semiconductor device as claimed in  claim 9 , wherein
 in case one of the second wirings is activated, channels electrically connecting the corresponding first and second impurity diffusion layers are formed in the corresponding first and second divided portions. 
 
     
     
       11. The semiconductor device as claimed in  claim 7 ,
 wherein 
 each of the transistors further includes an upper insulating film being arranged between a bottom surface of the corresponding second wiring and a top surface of the corresponding first impurity diffusion layer, and 
 a lower insulating film being arranged between a top surface of each of the corresponding second wiring and a bottom surface of the corresponding second impurity diffusion layer. 
 
     
     
       12. The semiconductor device as claimed in  claim 7 , further comprising capacitors being provided for each of the transistors, wherein
 each of the capacitors has an electrode electrically connected to the corresponding second impurity diffusion layer. 
 
     
     
       13. The semiconductor device as claimed in  claim 12 , wherein
 each of the first wirings is a bit line, and each of the second wirings is a word line. 
 
     
     
       14. A semiconductor device comprising: a semiconductor substrate; a plurality of bit lines each extending in a first direction; a plurality of word lines each extending in a second direction perpendicular to the first direction; a plurality of first impurity diffusion layers; a plurality of silicon pillars; and a plurality of transistors arranged at the intersections of the bit lines and the word lines in a matrix configuration, wherein each of the transistors includes one of the silicon pillars projecting perpendicularly from a main surface of the semiconductor substrate; one of the first impurity diffusion layers formed in a lower part of the silicon pillar; and a second impurity diffusion layer formed in an upper part of the silicon pillar, a central part of the silicon pillar is divided into a first divided portion and a second divided portion, the lower part of the silicon pillar being connected with both of the first and second divided portions, the upper part of the silicon pillar being connected with both of the first and second divided portions, each of the first impurity diffusion layers diffuses into the semiconductor substrate so as to be continuous between the silicon pillars adjoining in the first direction, each of the bit lines being constituted by the first impurity diffusion layers continuous in the first direction, and each of the word lines is arranged between the first and second divided portions of the corresponding transistors. 
     
     
       15. The semiconductor device as claimed in  claim 14 , wherein
 the word lines are not provided between the silicon pillars adjoining each other in the first direction. 
 
     
     
       16. The semiconductor device as claimed in  claim 14 , wherein
 the second impurity diffusion layers adjoining each other in the first direction are separated by an insulating film. 
 
     
     
       17. The semiconductor device as claimed in  claim 14 , wherein
 each of the transistors further includes a gate insulating film formed between the corresponding word line and each of the corresponding first and second divided portions, the corresponding word line constituting a gate electrode common to the corresponding first and second divided portions. 
 
     
     
       18. The semiconductor device as claimed in  claim 17 , wherein
 in case one of the second wirings is activated, channels electrically connecting the corresponding first and second impurity diffusion layers are formed in the corresponding first and second divided portions. 
 
     
     
       19. The semiconductor device as claimed in  claim 14 , wherein
 each of the transistors further includes an upper insulating film being arranged between a bottom surface of the corresponding word line and a top surface of the corresponding first impurity diffusion layer, and 
 a lower insulating film being arranged between a top surface of each of the corresponding word line and a bottom surface of the corresponding second impurity diffusion layer. 
 
     
     
       20. The semiconductor device as claimed in  claim 14 , further comprising capacitors being provided for each of the transistors, wherein
 each of the capacitors has an electrode electrically connected to the corresponding second impurity diffusion layer.