Methods of forming semiconductor memory devices having vertically stacked memory cells therein

Abstract

Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.

What is claimed is: 
     
       1. A method of forming a nonvolatile memory device, comprising:
 forming a first vertical stack of layers on a substrate, said first vertical stack of layers comprising a composite of at least a plurality of first material layers and a plurality of second material layers arranged as an alternating stack of first and second material layers comprising different materials; 
 forming a first opening extending through at least a plurality of the first material layers and at least a plurality of the second material layers within the first vertical stack of layers; 
 filling at least a portion of the first opening with a composite stack of a bulk sacrificial pattern and a capping sacrificial pattern on the bulk sacrificial pattern, said bulk and capping sacrificial patterns comprising different materials and said bulk sacrificial pattern comprising a polymerized material containing carbon; 
 forming a second vertical stack of layers of different materials on the first vertical stack of layers; 
 forming a second opening that extends through the second vertical stack of layers and exposes the capping sacrificial pattern within the first opening; and 
 removing the capping sacrificial pattern and the bulk sacrificial pattern through the second opening. 
 
     
     
       2. The method of  claim 1 , wherein the capping sacrificial pattern comprises a material that blocks diffusion of carbon therein. 
     
     
       3. The method of  claim 1 , wherein said forming a second opening and said removing the capping sacrificial pattern are performed within a single reaction chamber. 
     
     
       4. The method of  claim 3 , wherein said removing the bulk sacrificial pattern through the second opening comprises exposing the bulk sacrificial pattern to a reaction gas containing oxygen. 
     
     
       5. The method of  claim 3 , wherein said removing the bulk sacrificial pattern through the second opening comprises anisotropically dry etching the bulk sacrificial pattern using a reaction gas comprising oxygen. 
     
     
       6. The method of  claim 1 , wherein said forming a bulk sacrificial pattern in the first opening comprises depositing the bulk sacrificial pattern into the first opening using a spin-on coating process. 
     
     
       7. The method of  claim 6 , wherein depositing the bulk sacrificial pattern into the first opening using a spin-on coating process is followed by etching the deposited bulk sacrificial pattern for a sufficient duration to recess the bulk sacrificial pattern within the first opening; and wherein said forming a capping sacrificial pattern comprises depositing the capping sacrificial layer into a recess within the first opening. 
     
     
       8. The method of  claim 7 , wherein said forming a second vertical stack of layers is preceded by planarizing the capping sacrificial layer to thereby expose an upper surface of the first vertical stack of layers. 
     
     
       9. The method of  claim 1 , wherein said removing the capping sacrificial pattern and the bulk sacrificial pattern through the second opening is followed by lining sidewalls of the first and second openings with a semiconductor active pattern. 
     
     
       10. The method of  claim 9 , further comprising:
 selectively etching the second vertical stack of layers and the first vertical stack of layers in sequence to define a groove therein that exposes the substrate; and then 
 replacing the plurality of second material layers with gate patterns of nonvolatile memory cell transistors. 
 
     
     
       11. A method of forming a semiconductor memory device, the method comprising:
 forming a first stack structure including first dielectric layers and first material layers alternately and repeatedly stacked on a substrate; 
 forming a first opening penetrating the first stack structure; 
 forming a bulk sacrificial pattern and a capping sacrificial pattern sequentially stacked in the first opening, the bulk sacrificial pattern including a highly polymerized compound material containing carbon; 
 forming a second stack structure including second dielectric layers and second material layers alternately and repeatedly stacked on the first stack structure; 
 forming a second opening that penetrates the second stack structure to expose the capping sacrificial pattern; and 
 removing the capping sacrificial pattern and the bulk sacrificial pattern. 
 
     
     
       12. The method of  claim 11 , wherein the highly polymerized compound material containing carbon has an etch selectivity with respect to the first and second dielectric layers, the first and second material layers and the substrate. 
     
     
       13. The method of  claim 11 , wherein the capping sacrificial pattern is formed of a material having an etch selectivity with respect to the first and second dielectric layers, and the first and second material layers. 
     
     
       14. The method of  claim 11 , wherein forming the second opening comprises:
 forming a mask pattern on the second stack structure; and 
 etching the second stack structure using the mask pattern as an etch mask, 
 wherein etching the second stack structure and removing the capping sacrificial pattern are performed in a same reaction chamber. 
 
     
     
       15. The method of  claim 11 , wherein forming the bulk sacrificial pattern comprises:
 forming a bulk sacrificial layer filling the first opening on the first stack structure; and 
 etching a portion of the bulk sacrificial layer, 
 wherein etching the bulk sacrificial layer is performed until a top surface of the bulk sacrificial layer is located at a lower level than a top surface of the first stack structure. 
 
     
     
       16. The method of  claim 15 , wherein the bulk sacrificial layer is formed using a spin coating process. 
     
     
       17. The method of  claim 16 , wherein the bulk sacrificial layer is formed of a spin-on-hard mask layer. 
     
     
       18. The method of  claim 15 , wherein etching the bulk sacrificial layer is performed using a reaction gas including oxygen. 
     
     
       19. The method of  claim 11 , wherein forming the capping sacrificial pattern comprises:
 forming a capping sacrificial layer on the first stack structure; and 
 planarizing the capping sacrificial layer until a top surface of the first stack structure is exposed. 
 
     
     
       20. The method of  claim 11 , wherein removing the bulk sacrificial pattern is performed using a dry etching process that employs a reaction gas including oxygen as an etching gas.