P
US8447582B2ActiveUtilityPatentIndex 26

Variation distribution simulation apparatus and method, and recording medium

Assignee: FUJII FUMIEPriority: Sep 25, 2009Filed: Mar 23, 2010Granted: May 21, 2013
Est. expirySep 25, 2029(~3.2 yrs left)· nominal 20-yr term from priority
Inventors:FUJII FUMIEYOSHITOMI SADAYUKIWAKITA NAOKIITANO YUKA
G06F 30/367
26
PatentIndex Score
0
Cited by
19
References
20
Claims

Abstract

A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET. The apparatus includes a storage part configured to store an intermediate model expression that includes a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression being formed with a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter, a setting part configured to set information about the variable included in the intermediate model expression, a calculation part configured to calculate the set value of the SPICE parameter by using the information set in the setting part and the intermediate model expression stored in the storage part, and an output part configured to output process variation dependency of the semiconductor circuit.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A circuit simulation apparatus configured to calculate a set value of a SPICE parameter of a MOSFET suitable for use in carrying out a variation analysis on a semiconductor circuit comprising the MOSFET, the apparatus comprising:
 a storage device configured to store an intermediate model expression comprising a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression further comprising a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter; 
 a setting part configured to set information about the variable included in the intermediate model expression; 
 a calculation part configured to calculate the set value of the SPICE parameter by using the information set in the setting part and the intermediate model expression stored in the storage device; and 
 an output part configured to output process variation dependency of the semiconductor circuit. 
 
     
     
       2. The apparatus of  claim 1 , wherein
 the intermediate model expression comprises a variable comprising at least one of a channel concentration, a dimension of a gate, and a thickness of a gate insulator of the MOSFET, and 
 the calculation part is further configured to calculate a set value suitable for use in analyzing a variation in analog low-frequency characteristics of the semiconductor circuit. 
 
     
     
       3. The apparatus of  claim 2 , wherein the intermediate model expression comprises a representation of the expression (36): 
       
         
           
             
               
                 
                   
                     
                       
                         K_V 
                         TH 
                       
                       = 
                       
                         
                           
                             T 
                             OX 
                           
                           
                             T 
                             
                               OX 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               0 
                             
                           
                         
                         · 
                         
                           
                             ( 
                             
                               
                                 N 
                                 DEP 
                               
                               
                                 N 
                                 
                                   DEP 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   0 
                                 
                               
                             
                             ) 
                           
                           
                             1 
                             4 
                           
                         
                         · 
                         
                           
                             
                               
                                 W 
                                 o 
                               
                               · 
                               
                                 L 
                                 o 
                               
                             
                             
                               W 
                               · 
                               L 
                             
                           
                         
                       
                     
                     , 
                   
                 
                 
                   
                     ( 
                     36 
                     ) 
                   
                 
               
             
           
         
         where K_V TH  represents the intermediate model expression, L and W respectively represent a gate length and a gate width, each of which is the dimension of the gate, T OX  represents the thickness of the gate insulator, N DEP  represents the channel concentration, and L 0 , W 0 , T OX0 , and N DEP0  respectively represents nominal values of L, W, T OX , and N DEP , in a case where the SPICE parameter is a threshold voltage of the MOSFET. 
       
     
     
       4. The apparatus of  claim 1 , wherein
 the intermediate model expression comprises a variable comprising at least one of a resistivity of a gate electrode material, a resistivity of a substrate, and an impurity density in source and drain diffusion layers of the MOSFET, a thickness of an interconnect layer electrically connected to the MOSFET, and a thickness of an inter layer dielectric covering the MOSFET, and 
 the calculation part is further configured to calculate a set value suitable for use in analyzing a variation in analog radio-frequency characteristics or noise characteristics of the semiconductor circuit. 
 
     
     
       5. The apparatus of  claim 1 , wherein the intermediate model expression comprises a representation of the expression (37):
   μ e= 7022.7−160·log( N   DEP /1.3)  (37),
 
 where μe represents the intermediate model expression, and N DEP  represents a channel concentration of the MOSFET, in a case where the SPICE parameter is an electron mobility in the MOSFET. 
 
     
     
       6. The apparatus of  claim 1 , wherein the intermediate model expression comprises a representation of the expression (38):
   μ h= 190.8−418.81·log( N   DEP )  (38),
 
 where μh represents the intermediate model expression, and N DEP  represents a channel concentration of the MOSFET, in a case where the SPICE parameter is a hole mobility in the MOSFET. 
 
     
     
       7. The apparatus of  claim 1 , wherein
 the intermediate model expression comprises an association between the set value of the SPICE parameter and a nominal value of the SPICE parameter. 
 
     
     
       8. The apparatus of  claim 7 , wherein
 the calculation part is further configured to represent the set value of the SPICE parameter by a product of the nominal value of the SPICE parameter and the intermediate model expression. 
 
     
     
       9. The apparatus of  claim 7 , wherein
 the intermediate model expression is formed and stored in the storage device before the information about the variable included in the intermediate model expression is set in the setting part. 
 
     
     
       10. The apparatus of  claim 1 , wherein
 the information set in the setting part comprises a nominal value and a standard deviation of the variable in the intermediate model expression. 
 
     
     
       11. The apparatus of  claim 1 , wherein
 the calculation part is configured to calculate the set value of the SPICE parameter by using a nominal value of the SPICE parameter. 
 
     
     
       12. A circuit simulation method of calculating a set value of a SPICE parameter of a MOSFET suitable for use in carrying out a variation analysis on a semiconductor circuit comprising the MOSFET, the method being performed by information processing apparatus and comprising:
 storing, in the information processing apparatus, an intermediate model expression that comprising a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression being further comprising a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter; 
 setting, in the information processing apparatus, information about the variable included in the intermediate model expression; 
 calculating the set value of the SPICE parameter by using the information and the intermediate model expression; and 
 outputting process variation dependency of the semiconductor circuit. 
 
     
     
       13. The method of  claim 12 , wherein
 the intermediate model expression comprises a variable comprising at least one of a channel concentration, a dimension of a gate, and a thickness of a gate insulator of the MOSFET, and 
 calculating comprises calculating a set value suitable for use in analyzing a variation in analog low-frequency characteristics of the semiconductor circuit. 
 
     
     
       14. The method of  claim 12 , wherein
 the intermediate model expression comprises a variable comprising at least one of a resistivity of a gate electrode material, a resistivity of a substrate, and an impurity density in source and drain diffusion layers of the MOSFET, a thickness of an interconnect layer electrically connected to the MOSFET, and a thickness of an inter layer dielectric covering the MOSFET, and 
 calculating comprises calculating a set value suitable for use in analyzing a variation in analog radio-frequency characteristics or noise characteristics of the semiconductor circuit. 
 
     
     
       15. The method of  claim 12 , wherein
 the intermediate model expression comprises an association between the set value of the SPICE parameter and a nominal value of the SPICE parameter. 
 
     
     
       16. The method of  claim 15 , wherein
 the set value of the SPICE parameter comprises a representation of a product of the nominal value of the SPICE parameter and the intermediate model expression. 
 
     
     
       17. The method of  claim 12 , wherein
 the intermediate model expression is formed and stored in the information processing apparatus before the information about the variable included in the intermediate model expression is set in the setting part. 
 
     
     
       18. The method of  claim 12 , wherein
 the information comprises a nominal value and a standard deviation of the variable included in the intermediate model expression. 
 
     
     
       19. The method of  claim 12 , wherein calculating the set value of the SPICE parameter comprises using a nominal value of the SPICE parameter. 
     
     
       20. A computer readable non-transitory storage medium comprising computer executable instructions that, when executed on a computer, implement a circuit simulation method of calculating a set value of a SPICE parameter of a MOSFET suitable for use in carrying out a variation analysis on a semiconductor circuit comprising the MOSFET, the method comprising:
 reading, from a storage device, an intermediate model expression that comprising a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression comprising a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter; 
 reading, from a setting part, information about the variable in the intermediate model expression; 
 calculating the set value of the SPICE parameter by using the information read from the setting part and the intermediate model expression read from the storage device; and 
 outputting process variation dependency of the semiconductor circuit.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.