Array substrate for fringe field switching mode liquid crystal display and method of manufacturing the same

Abstract

A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose a first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness less than the first thickness; and performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode.

What is claimed is: 
     
       1. A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display, the method comprising:
 forming a thin film transistor in a pixel region on a substrate; 
 forming a first passivation layer on the thin film transistor; 
 forming a common electrode on the first passivation layer; 
 forming a second passivation layer on the common electrode; 
 forming an auxiliary insulating layer on the second passivation layer and having a first thickness; 
 forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; 
 etching the auxiliary insulating layer, the second passivation layer and the first passivation layer using the first and second photoresist patterns as an etching mask to form a drain contact hole exposing a drain electrode of the thin film transistor; 
 performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; 
 performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; 
 forming a transparent conductive material layer on the substrate having the first photoresist pattern and having a fourth thickness less than the first thickness; and 
 performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode as a remaining portion of the transparent conductive material layer. 
 
     
     
       2. The method according to  claim 1 , wherein the second passivation layer and the auxiliary insulating layer are made of the same material and sequentially formed in the same chamber of a chemical vapor deposition apparatus. 
     
     
       3. The method according to  claim 2 , wherein the second passivation layer is formed in the chamber under a first condition that a temperature is about 210 degrees Celsius to about 230 degrees Celsius, a pressure is about 1000 mT to about 1200 mT, a power is about 700 W to about 900 W, and gas flow rates of ammonia (NH 3 ) and silane (SiH 4 ) flowing in the chamber are about 580 sccm to about 700 sccm and about 90 sccm to about 120 sccm, respectively, and wherein the auxiliary insulating layer is formed in the chamber under a second condition that a temperature is about 210 degrees Celsius to about 230 degrees Celsius, a pressure is about 1700 mT to about 1900 mT, a power is about 1200 W to about 1400 W, and gas flow rates of ammonia (NH 3 ) and silane (SiH 4 ) flowing in the chamber are about 280 sccm to about 360 sccm and about 140 sccm to about 180 sccm, respectively. 
     
     
       4. The method according to  claim 3 , wherein the dry etching is an isotropic dry etching and is performed in a chamber of a dry etching apparatus under a condition that a pressure is about 140 mT to about 160 mT, a power is about 270 W to about 330 W, and gas flow rates of sulfur hexafluoride (SF 6 ), oxygen (O 2 ), helium (He), and chlorine (Cl 2 ) are about 100 sccm to about 150 sccm, about 30 sccm, about 30 sccm, and about 30 sccm, respectively. 
     
     
       5. The method according to  claim 1 , wherein the common electrode is formed substantially all over a display region with an opening corresponding to the thin film transistor, or is formed individually in each pixel region and connected to a common electrode in a neighboring pixel region through a connection pattern. 
     
     
       6. The method according to  claim 1 , wherein forming the thin film transistor includes:
 forming an amorphous silicon layer on the substrate; 
 crystallizing the amorphous silicon layer into a polysilicon layer; 
 patterning the polysilicon layer into a semiconductor layer; 
 forming a gate insulating layer on the semiconductor layer; 
 forming a gate electrode on the gate insulating layer and corresponding to a center portion of the semiconductor layer; 
 impurity-doping the semiconductor layer using the gate electrode as a doping mask to form an ohmic contact layer; 
 forming an inter-layered insulating film on the gate electrode and exposing the ohmic contact layer; and 
 forming source and drain electrodes on the inter-layered insulating film and each contacting the ohmic contact layer. 
 
     
     
       7. The method according to  claim 6 , further comprising forming a light-blocking layer corresponding to the thin film transistor and a buffer layer on the light-blocking layer before forming the amorphous silicon layer. 
     
     
       8. The method according to  claim 1 , wherein forming the thin film transistor includes:
 forming a gate electrode on the substrate; 
 forming a gate insulating layer on the gate electrode; 
 forming a semiconductor layer on the gate insulating layer and including an active layer of intrinsic amorphous silicon, and an ohmic contact layer of impurity-doped amorphous silicon on the active layer; and 
 forming source and drain electrodes on the semiconductor layer. 
 
     
     
       9. The method according to  claim 6  or  8 , further comprising forming a gate line connected to the gate electrode in the same step of forming the gate electrode, and forming a data line connected to the source electrode in the same step of forming the source and drain electrodes. 
     
     
       10. The method according to  claim 9 , wherein the pixel electrode, the insulating pattern and the data line are bent and symmetrical with respect to a center portion of each pixel region.