Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells; 
 a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring; and 
 a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring disposed above the first wiring, 
 the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring. 
 
     
     
       2. The semiconductor memory device according to  claim 1 ,
 wherein the plurality of memory cells are formed on an upper surface of the first wiring at a first pitch, and 
 the thickness of the first wiring is smaller than the thickness of the second wiring. 
 
     
     
       3. The semiconductor memory device according to  claim 1 ,
 wherein an amount of digging from a surface of the second wiring of a connecting portion of the second wiring connected to the second via is larger than that from a surface of the first wiring of a connecting portion of the first wiring connected to the first via. 
 
     
     
       4. The semiconductor memory device according to  claim 1 ,
 wherein a material of the first wiring is a material made by reducing a first seed using a first reducing gas, and 
 a material of the second wiring is a material made by reducing the first seed using a second reducing gas different from the first reducing gas. 
 
     
     
       5. The semiconductor memory device according to  claim 4 ,
 wherein the first seed is a tungsten seed, 
 the first reducing gas is B 2 H 6 , and 
 the second reducing gas is SiH 4 . 
 
     
     
       6. The semiconductor memory device according to  claim 1 ,
 wherein the first and second wirings are one of a plurality of word lines and bit lines crossing each other, and 
 the memory cells are provided in crossing portions of the word lines and the bit lines. 
 
     
     
       7. The semiconductor memory device according to  claim 1 ,
 wherein each of the memory cells has a variable resistance element and a non-ohmic element connected in series. 
 
     
     
       8. A semiconductor memory device comprising:
 a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells; 
 a pillar-shaped first via extending in a stack direction and having side surfaces connected to a first wiring; and 
 a pillar-shaped second via extending in the stack direction and having side surfaces connected to a second wiring, 
 a length from the second wiring to a bottom surface of the second via being longer than that from the first wiring to a bottom surface of the first via, 
 the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring. 
 
     
     
       9. The semiconductor memory device according to  claim 8 ,
 wherein the plurality of memory cells are formed on an upper surface of the first wiring at a first pitch, and 
 the thickness of the first wiring is smaller than the thickness of the second wiring. 
 
     
     
       10. The semiconductor memory device according to  claim 8 ,
 wherein an amount of digging from a surface of the second wiring of a connecting portion of the second wiring connected to the second via is larger than that from a surface of the first wiring of a connecting portion of the first wiring connected to the first via. 
 
     
     
       11. The semiconductor memory device according to  claim 8 ,
 wherein a material of the first wiring is a material made by reducing a first seed using a first reducing gas, and 
 a material of the second wiring is a material made by reducing the first seed using a second reducing gas different from the first reducing gas. 
 
     
     
       12. The semiconductor memory device according to  claim 11 ,
 wherein the first seed is a tungsten seed, 
 the first reducing gas is B 2 H 6 , and 
 the second reducing gas is SiH 4 . 
 
     
     
       13. The semiconductor memory device according to  claim 8 ,
 wherein the plurality of selective wirings are a plurality of word lines and bit lines crossing each other, and 
 the memory cells are provided in crossing portions of the word lines and the bit lines. 
 
     
     
       14. The semiconductor memory device according to  claim 8 ,
 wherein each of the memory cells has a variable resistance element and a non-ohmic element connected in series.