Thin film transistor with offset structure and electrodes in a symmetrical arrangement

Abstract

A thin film transistor (TFT) having an offset structure is disclosed. The TFT maintains a sufficiently low “off” current and a sufficiently high “on” current. The TFT includes an active region. The active region includes a gate electrode; an active layer that overlaps with the gate electrode; a gate insulating layer between the gate electrode and the active layer; and a source/drain electrode layer including source/drain electrodes that are electrically connected to the active region. Some of the source/drain electrodes overlap partially with the gate electrode. Other of the source/drain electrodes are offset from the gate electrode. The source/drain electrodes and the gate electrode are in a symmetrical arrangement.

What is claimed is: 
     
       1. A thin film transistor (TFT) comprising an active region divided into a first active region and a second active region, the active region comprising:
 a gate electrode; 
 an active layer comprising a first active layer corresponding to the first active region, and a second active layer corresponding to the second active region, the first active layer and the second active layer overlapping with the gate electrode; 
 a gate insulating layer between the gate electrode and the active layer; and 
 a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the first active layer, and a third source/drain electrode and a fourth source/drain electrode that are electrically connected to the second active layer, 
 wherein:
 two source/drain electrodes selected from among the first to fourth source/drain electrodes overlap partially with the gate electrode, 
 an other two source/drain electrodes from among the first to fourth source/drain electrodes are offset from the gate electrode, and 
 the first to fourth source/drain electrodes and the gate electrode are in a symmetrical arrangement. 
 
 
     
     
       2. The TFT of  claim 1 , wherein:
 the first and third source/drain electrodes are electrically connected to each other so that a same voltage is applied to the first and third source/drain electrodes, and 
 the second and fourth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the second and fourth source/drain electrodes. 
 
     
     
       3. The TFT of  claim 2  wherein:
 the first source/drain electrode and the third source/drain electrode are connected to each other, and 
 the second source/drain electrode and the fourth source/drain electrode are connected to each other. 
 
     
     
       4. A TFT comprising two TFTs as claimed in  claim 3 , wherein corresponding source/drain and gate electrodes of the two TFTs are connected in a symmetrical arrangement to function as a single TFT. 
     
     
       5. The TFT of  claim 1 , wherein the active layer comprises a material selected from the group consisting of amorphous silicon, polycrystalline silicon, micro crystalline silicon, an oxide semiconductor, an organic semiconductor, and combinations thereof. 
     
     
       6. The TFT of  claim 1 , wherein the active region further comprises an ohmic contact layer between the active layer and the source/drain electrode layer. 
     
     
       7. The TFT of  claim 1 , wherein:
 the first active layer comprises a first source/drain region corresponding to the first source/drain electrode, a second source/drain region corresponding to the second source/drain electrode, and a first channel region between the first source/drain region and the second source/drain region, and 
 the second active layer comprises a third source/drain region corresponding to the third source/drain electrode, a fourth source/drain region corresponding to the fourth source/drain electrode, and a second channel region between the third source/drain region and the fourth source/drain region. 
 
     
     
       8. The TFT of  claim 7 , wherein:
 the first channel region comprises a first offset region that does not overlap with any of the gate electrode, the first source/drain electrode, and the second source/drain electrode, and 
 the second channel region comprises a second offset region that does not overlap with any of the gate electrode, the third source/drain electrode, and the fourth source/drain electrode. 
 
     
     
       9. The TFT of  claim 1 , wherein the source/drain electrode layer in the second active region is rotationally symmetrical to the source/drain electrode layer in the first active region. 
     
     
       10. The TFT of  claim 9 , wherein:
 one of the first source/drain electrode and the second source/drain electrode overlaps with the gate electrode, and 
 an other of the first source/drain electrode and the second source/drain electrode is offset from the gate electrode. 
 
     
     
       11. The TFT of  claim 1 , wherein the first active region and the second active region are insulated from each other. 
     
     
       12. The TFT of  claim 1 , wherein the gate electrode comprises a first gate electrode and a second gate electrode that are parallel with each other. 
     
     
       13. The TFT of  claim 12 , wherein:
 the first and third source/drain electrodes are electrically connected to each other so that a same voltage is applied to the first and third source/drain electrodes, and 
 the second and fourth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the second and fourth source/drain electrodes. 
 
     
     
       14. The TFT of  claim 12 , wherein the source/drain electrode layer in the second active region is rotationally symmetrical to the source/drain electrode layer in the first active region. 
     
     
       15. The TFT of  claim 14 , wherein:
 one of the first to fourth source/drain electrodes overlaps partially with the first gate electrode, and 
 an other of the first to fourth source/drain electrodes overlaps partially with the second gate electrode. 
 
     
     
       16. The TFT of  claim 12 , wherein a width of the first gate electrode that overlaps with the second active layer is smaller than a width of the first gate electrode that overlaps with the first active region. 
     
     
       17. The TFT of  claim 12 , wherein the active region further comprises an offset electrode overlapping with a region between the first gate electrode and the second gate electrode, the offset electrode being insulated from the active layer. 
     
     
       18. The TFT of  claim 17 , wherein the offset electrode comprises:
 a first offset electrode overlapping with a region between the first and second source/drain electrodes, the first offset electrode being insulated from the first active layer; and 
 a second offset electrode overlapping with a region between the third and fourth source/drain electrodes, the second offset electrode being insulated from the second active layer. 
 
     
     
       19. The TFT of  claim 17 , wherein:
 the first and third source/drain electrodes are electrically connected to each other so that a same voltage is applied to the first and third source/drain electrodes, and 
 the second and fourth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the second and fourth source/drain electrodes. 
 
     
     
       20. The TFT of  claim 17 , wherein the offset electrode is electrically connected to the first gate electrode and the second gate electrode. 
     
     
       21. The TFT of  claim 12 , wherein the first active region and the second active region are insulated from each other. 
     
     
       22. A thin film transistor (TFT) comprising an active region divided into a first active region, a second active region, and a third active region, the active region comprising:
 a gate electrode; 
 an active layer comprising a first active layer corresponding to the first active region, a second active layer corresponding to the second active region, and a third active layer corresponding to the third active region, the first active layer, the second active layer, and the third active layer overlapping with the gate electrode; 
 a gate insulating layer between the gate electrode and the active layer; and 
 a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the first active layer, a third source/drain electrode and a fourth source/drain electrode that are electrically connected to the second active layer, and a fifth source/drain electrode and a sixth source/drain electrode that are electrically connected to the third active layer, 
 wherein:
 two source/drain electrodes selected from among the first to fourth source/drain electrodes overlap partially with the gate electrode, 
 other two source/drain electrodes from among the first to fourth source/drain electrodes are offset from the gate electrode, and 
 the first to sixth source/drain electrodes and the gate electrode are in a symmetrical arrangement. 
 
 
     
     
       23. The TFT of  claim 22 , wherein:
 the first, third, and fifth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the first, third, and fifth source/drain electrodes, and 
 the second, fourth, and sixth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the second, fourth, and sixth source/drain electrodes. 
 
     
     
       24. The TFT of  claim 22 , wherein the source/drain electrode layer in the third active region is symmetrical to the source/drain electrode layer in the first active region. 
     
     
       25. The TFT of  claim 22 , wherein:
 the first source/drain electrode and the second source/drain electrode overlap partially with the gate electrode, and 
 the third source/drain electrode and the fourth source/drain electrode are offset from the gate electrode. 
 
     
     
       26. The TFT of  claim 22 , wherein:
 the first active layer comprises a first source/drain region corresponding to the first source/drain electrode, a second source/drain region corresponding to the second source/drain electrode, and a first channel region between the first source/drain region and the second source/drain region, 
 the second active layer comprises a third source/drain region corresponding to the third source/drain electrode, a fourth source/drain region corresponding to the fourth source/drain electrode, and a second channel region between the third source/drain region and the fourth source/drain region, and 
 the third active layer comprises a fifth source/drain region corresponding to the fifth source/drain electrode, a sixth source/drain region corresponding to the sixth source/drain electrode, and a third channel region between the fifth source/drain region and the sixth source/drain region. 
 
     
     
       27. The TFT of  claim 26 , wherein the second channel region comprises an offset region that does not overlap with any of the gate electrode, the third source/drain electrode, and the fourth source/drain electrode. 
     
     
       28. The TFT of  claim 27 , wherein the source/drain electrode layer in the first active region, the source/drain electrode layer in the second active region, and the source/drain electrode layer in the third active region are symmetrical along an axis of symmetry. 
     
     
       29. The TFT of  claim 22 , wherein a width of the gate electrode that overlaps with the second active layer is smaller than a width of the gate electrode that overlaps with the first and third active regions. 
     
     
       30. The TFT of  claim 22 , wherein the first to third active regions are insulated from one another. 
     
     
       31. A thin film transistor (TFT) comprising an active region divided into a first active region, a second active region, a third active region, and a fourth active region, the active region comprising:
 a gate electrode; 
 an active layer comprising a first active layer corresponding to the first active region, a second active layer corresponding to the second active region, a third active layer corresponding to the third active region, and a fourth active layer corresponding to the fourth active region, the first active layer, the second active layer, the third active layer, and the fourth active layer overlapping with the gate electrode; 
 a gate insulating layer between the gate electrode and the active layer; and 
 a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the first active layer, a third source/drain electrode and a fourth source/drain electrode that are electrically connected to the second active layer, a fifth source/drain electrode and a sixth source/drain electrode that are electrically connected to the third active layer, and a seventh source/drain electrode and an eighth source/drain electrode that are electrically connected to the fourth active layer, 
 wherein:
 two source/drain electrodes selected from among the third to sixth source/drain electrodes overlap partially with the gate electrode, 
 other two source/drain electrodes from among the third to sixth source/drain electrodes are offset from the gate electrode, and 
 the first to eighth source/drain electrodes and the gate electrode are in a symmetrical arrangement. 
 
 
     
     
       32. The TFT of  claim 31 , wherein:
 the first, third, fifth, and seventh source/drain electrodes are electrically connected to each other so that a same voltage is applied to the first, third, fifth, and seventh source/drain electrodes, and 
 the second, fourth, sixth, and eighth source/drain electrodes are electrically connected to each other so that a same voltage is applied to the second, fourth, sixth, and eighth source/drain electrodes. 
 
     
     
       33. The TFT of  claim 31 , wherein:
 the first active layer comprises a first source/drain region corresponding to the first source/drain electrode, a second source/drain region corresponding to the second source/drain electrode, and a first channel region between the first source/drain region and the second source/drain region, 
 the second active layer comprises a third source/drain region corresponding to the third source/drain electrode, a fourth source/drain region corresponding to the fourth source/drain electrode, and a second channel region between the third source/drain region and the fourth source/drain region, 
 the third active layer comprises a fifth source/drain region corresponding to the fifth source/drain electrode, a sixth source/drain region corresponding to the sixth source/drain electrode, and a third channel region between the fifth source/drain region and the sixth source/drain region, and 
 the fourth active layer comprises a seventh source/drain region corresponding to the seventh source/drain electrode, an eighth source/drain region corresponding to the eighth source/drain electrode, and a fourth channel region between the seventh source/drain region and the eighth source/drain region. 
 
     
     
       34. The TFT of  claim 33 , wherein:
 the second channel region comprises a first offset region that does not overlap with any of the gate electrode, the third source/drain electrode, and the fourth source/drain electrode, and 
 the third channel region comprises a second offset region that does not overlap with any of the gate electrode, the fifth source/drain electrode, and the sixth source/drain electrode. 
 
     
     
       35. The TFT of  claim 34 , wherein:
 the source/drain electrode layer in the third active region is rotationally symmetrical to the source/drain electrode layer in the second active region, and 
 the source/drain electrode layer in the fourth active region is symmetrical to the source/drain electrode layer in the first active region. 
 
     
     
       36. The TFT of  claim 35 , wherein the first source/drain electrode and the second source/drain electrode overlap partially with the gate electrode. 
     
     
       37. The TFT of  claim 35 , wherein:
 one of the third source/drain electrode and the fourth source/drain electrode overlaps with the gate electrode, and 
 an other of the third source/drain electrode and the fourth source/drain electrode is offset from the gate electrode. 
 
     
     
       38. The TFT of  claim 31 , wherein a width of the gate electrode that overlaps with the second and third active regions is smaller than a width of the gate electrode that overlaps with the first and fourth active regions. 
     
     
       39. The TFT of  claim 31 , wherein the first to fourth active regions are insulated from one another. 
     
     
       40. A thin film transistor (TFT) comprising an active region comprising:
 a gate electrode comprising a first gate electrode and a second gate electrode that are parallel with each other; 
 an active layer overlapping with the first gate electrode and the second gate electrode, and comprising a first gate region corresponding to the first gate electrode, a second gate region corresponding to the second gate electrode, and an offset region extending from the first gate region to the second gate region; 
 a gate insulating layer between the gate electrode and the active layer; and 
 a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the active layer, 
 wherein:
 the first source/drain electrode overlaps partially with the first gate electrode, 
 the second source/drain electrode overlaps partially with the second gate electrode, 
 the offset region does not overlap with any of the first gate electrode, the second gate electrode, the first source/drain electrode, and the second source/drain electrode, and 
 the first and second source/drain electrodes and the gate electrode are in a symmetrical arrangement. 
 
 
     
     
       41. The TFT of  claim 40 , wherein the active region further comprises an offset electrode overlapping with a region between the first gate electrode and the second gate electrode, the offset electrode being insulated from the active layer. 
     
     
       42. The TFT of  claim 41 , wherein the offset electrode is electrically connected to the first gate electrode and the second gate electrode. 
     
     
       43. The TFT of  claim 40 , wherein the active layer comprises a first source/drain region corresponding to the first source/drain electrode, a second source/drain region corresponding to the second source/drain electrode, and a channel region between the first source/drain region and the second source/drain region. 
     
     
       44. The TFT of  claim 43 , wherein the channel region comprises the offset region.