Memory device and method for making same

Abstract

An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.

What is claimed is: 
     
       1. A memory array, comprising:
 a plurality of memory cells arranged along a first direction and a second direction, each of said cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor, said heterojunction bipolar transistor of each of said memory cells being an access device, said heterojunction bipolar transistor of each of said memory cells including a collector region, said collector regions being spaced apart from each other along said first direction and along said second direction. 
 
     
     
       2. The memory array of  claim 1 , wherein said heterojuction bipolar transistor is a SiGe heterojunction bipolar transistor including a SiGe base layer. 
     
     
       3. The memory array of  claim 2 , wherein said SiGe base includes the element carbon. 
     
     
       4. The memory array of  claim 1 , said transistor is a SiGe:C heterojunction bipolar transistor including a SiGe:C base layer. 
     
     
       5. The memory array of  claim 1 , wherein said memory element is electrically coupled in series with said transistor. 
     
     
       6. The memory array of  claim 1 , wherein each of said transistors includes an emitter region and a base region, said memory element being electrically coupled between a bitline and said emitter region, said base region electrically coupled to a wordline. 
     
     
       7. The memory array of  claim 1 , wherein said collector regions are spaced apart from each other along said first direction by first insulating trenches and wherein said collector regions are spaced apart from each other along said second direction by second insulating trenches. 
     
     
       8. The memory array of  claim 7  wherein said first insulating trenches are oriented in said second direction and said second insulating trenches are oriented in said first direction. 
     
     
       9. The memory array of  claim 7 , wherein said insulating trenches directly contact a buried layer, said buried layer underlying said collector regions. 
     
     
       10. The memory array of  claim 1 , wherein said first direction is perpendicular to said second direction. 
     
     
       11. The memory array of  claim 1 , further comprising:
 a plurality of wordlines; and 
 a plurality of bitlines, 
 
       wherein said first direction is parallel to said wordlines and said second direction is parallel to said bitlines. 
     
     
       12. The memory array of  claim 1 , wherein said memory array is configured in a NOR architecture. 
     
     
       13. A memory array, comprising:
 a plurality of memory cells, each of said cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor, said heterojunction bipolar transistor of each of said memory cells being an access device, said heterojunction bipolar transistor of each of said memory cells including a collector region, each of said collector regions being spaced apart from all other collector regions of said memory array. 
 
     
     
       14. The memory array of  claim 13 , wherein said collector regions are spaced apart by insulating trenches. 
     
     
       15. The memory array of  claim 14 , wherein said insulating trenches directly contact a buried layer, said buried layer underlying said collector regions. 
     
     
       16. The memory array of  claim 13 , wherein said heterojuction bipolar transistor is a SiGe heterojunction bipolar transistor including a SiGe base layer. 
     
     
       17. The memory array of  claim 16 , wherein said SiGe base includes the element carbon. 
     
     
       18. The memory array of  claim 13 , said transistor is a SiGe:C heterojunction bipolar transistor including a SiGe:C base layer. 
     
     
       19. The memory array of  claim 13 , wherein said memory element is electrically coupled in series with said transistor. 
     
     
       20. The memory array of  claim 13 , wherein each of said transistors includes an emitter region and a base region, said memory element being electrically coupled between a bitline and said emitter region, said base region electrically coupled to a wordline. 
     
     
       21. The memory array of  claim 13 , wherein said memory array is configured in a NOR architecture. 
     
     
       22. The memory array of  claim 13 , wherein each of said collector regions being spaced apart from all other collector regions of said memory array by a dielectric. 
     
     
       23. The memory array of  claim 22 , wherein said dielectric directly contacts a buried layer, said buried layer underlying said collector regions. 
     
     
       24. The memory array of  claim 23 , wherein said buried layer electrically couples each of said collector regions to a common potential. 
     
     
       25. The memory array of  claim 1 , wherein said programmable resistance memory element of each of said cells is a phase-change memory element. 
     
     
       26. The memory array of  claim 13 , wherein said programmable resistance memory element of each of said cells is a phase-change memory element.