System and method of transistor switch biasing in a high power semiconductor switch

Abstract

A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.

What is claimed is: 
     
       1. A switch circuit comprising:
 a first transistor switch; 
 a second transistor switch; 
 biasing circuitry including a first resistance and a second resistance and configured to receive a high control voltage and a low control voltage and to provide an on-state bias voltage to the first transistor switch and an off-state bias voltage to the second transistor switch, the on-state bias voltage being a difference between a product of the first resistance and the high control voltage and a product of the second resistance and the low control voltage, the off-state bias voltage being a difference between a product of the first resistance and the low control voltage and a product of the second resistance and the high control voltage, the off-state bias voltage having a magnitude that is different than a magnitude of the on-state bias voltage by an amount sufficient to yield at least one of a harmonic emission associated with the switch circuit that is less than a selected emission level and a linearity associated with the switch circuit that is greater than a selected linearity level. 
 
     
     
       2. The switch circuit of  claim 1  wherein the magnitude of the off-state bias voltage is less than the magnitude of the on-state bias voltage. 
     
     
       3. The switch circuit of  claim 1  wherein the harmonic emission associated with the switch circuit includes a spurious harmonic emission from the second transistor switch in its off state. 
     
     
       4. The switch circuit of  claim 1  wherein the magnitude difference between the on-state bias voltage and the off-state bias voltage is selected to yield both of the harmonic emission being less than the selected emission level and the linearity being greater than the selected linearity level. 
     
     
       5. The switch circuit of  claim 1  wherein the bias voltage includes a gate to source/drain bias voltage (Vgsd). 
     
     
       6. The switch circuit of  claim 5  wherein the off-state Vgsd level includes a value that is a fixed fraction of the on-state Vgsd level. 
     
     
       7. The switch circuit of  claim 5  wherein each of the first and second transistor switches includes a silicon-on-insulator (SOI) field-effect transistor (FET). 
     
     
       8. The switch circuit of  claim 7  wherein the on-state Vgsd level is between 2.0 V and 2.5 V, and the off-state Vgsd level is between 1.1 V and 1.5 V. 
     
     
       9. The switch circuit of  claim 5  wherein the biasing circuitry is configured to provide the on-state Vgsd to the first transistor switch by biasing a gate of the first transistor switch with an on-state gate voltage that is a fraction of a high system control voltage, and biasing a source-drain of the first transistor switch with an on-state source-drain voltage that is a fraction of a low system control voltage. 
     
     
       10. The switch circuit of  claim 9  wherein the biasing circuitry is further configured to provide the off-state Vgsd to the second transistor switch by biasing a gate of the second transistor switch with an off-state gate voltage that is a fraction of the low system control voltage, and biasing a source-drain of the second transistor switch with an off-state source-drain voltage that is a fraction of the high system control voltage. 
     
     
       11. The switch circuit of  claim 10  wherein the biasing circuitry includes at least one voltage divider circuit for providing the fractional values of the high and low system control voltages. 
     
     
       12. A wireless device comprising:
 an antenna; 
 a transmitter circuit; 
 a receiver circuit; and 
 a switching circuit that couples the transmitter circuit and the receiver circuit with the antenna so as to facilitate transmission and reception of wireless signals, the switching circuit including a first transistor switch, a second transistor switch, and biasing circuitry including a first resistance and a second resistance and configured to receive a high control voltage and a low control voltage and to provide an on-state bias voltage to the first transistor switch and an off-state bias voltage to the second transistor switch, the on-state bias voltage being a difference between a product of the first resistance and the high control voltage and a product of the second resistance and the low control voltage, the off-state bias voltage being a difference between a product of the first resistance and the low control voltage and a product of the second resistance and the high control voltage, the off-state bias voltage having a magnitude that is different than a magnitude of the on-state bias voltage by an amount sufficient to yield at least one of a harmonic emission associated with the switch circuit that is less than a selected emission level and a linearity associated with the switch circuit that is greater than a selected linearity level. 
 
     
     
       13. The wireless device of  claim 12  wherein the switching circuit includes a semiconductor-based transmit-receive switch. 
     
     
       14. The wireless device of  claim 12  wherein the transmitter circuit and the receiver circuit are parts of a transmit-receive circuit. 
     
     
       15. A method for biasing transistor switches, the method comprising:
 providing a difference between a product of a first resistance and a high control voltage and a product of a second resistance and a low control voltage as an on-state bias voltage to a first transistor switch; and 
 providing a difference between a product of the first resistance and the low control voltage and a product of the second resistance and the high control voltage as an off-state bias voltage to a second transistor switch, the off-state bias voltage having a magnitude that is different than a magnitude of the on-state bias voltage by an amount sufficient to yield at least one of a harmonic emission that is less than a selected emission level and a linearity that is greater than a selected linearity level. 
 
     
     
       16. The method of  claim 15  wherein the magnitude of the off-state bias voltage is less than the magnitude of the on-state bias voltage. 
     
     
       17. The method of  claim 15  wherein the harmonic emission includes a spurious harmonic emission from the second transistor switch in its off state. 
     
     
       18. The method of  claim 15  wherein the magnitude difference between the on-state bias voltage and the off-state bias voltage is selected to yield both of the harmonic emission being less than the selected emission level and the linearity being greater than the selected linearity level. 
     
     
       19. The method of  claim 15  wherein the bias voltage includes a gate to source/drain bias voltage (Vgsd). 
     
     
       20. The method of  claim 19  wherein the on-state Vgsd level includes a maximum potential difference between a gate and either of a source or a drain that is within reliability and operating constraints.