Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping

Abstract

A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

The invention claimed is: 
     
       1. A method, comprising:
 masking a surface of a layer on a semiconductor substrate, the layer comprising silicon or silicon-germanium, to define an unmasked area of the layer; 
 implanting a Boron dopant into said unmasked area of the layer to produce a surface region of the layer doped with Boron; 
 removing the masking to reveal a non-Boron doped surface region of the layer; 
 baking the semiconductor substrate to passivate the semiconductor substrate; 
 wherein baking comprises baking at a temperature which is below a temperature such that passivation is not achieved in the surface region doped with Boron but passivation is achieved in the non-Boron doped surface region; 
 performing a deposition on the surface of the layer in the absence of a mask which results in selective growth of silicon or silicon-germanium over the passivated non-Boron doped surface region to form a first region of the layer having a first thickness and wherein growth is suppressed over the non-passivated surface region doped with Boron to form a second region of the layer having a second thickness less than the first thickness. 
 
     
     
       2. The method of  claim 1 , wherein surface region doped with Boron has a Boron dopant concentration of at least 1×10 19  cm −3 . 
     
     
       3. The method of  claim 1 , wherein the layer of the semiconductor substrate comprises one or more gate lines. 
     
     
       4. The method of  claim 1  further comprising exposing to a cleaning solution after implanting and before baking. 
     
     
       5. The method of  claim 4 , wherein the cleaning solution is hydrofluoridic acid. 
     
     
       6. The method of  claim 1 , wherein said temperature for baking comprises a temperature below or equal to 800° Centigrade. 
     
     
       7. The method of  claim 1 , further comprising:
 masking said unmasked area of the layer which is Boron doped; and 
 implanting into the non-Boron doped surface region a dopant other than Boron. 
 
     
     
       8. The method of  claim 7 , wherein the dopant other than Boron is Arsenic or Phosphorus. 
     
     
       9. The method of  claim 1 , wherein baking is performed in a passivating H 2  ambient atmosphere. 
     
     
       10. The method of  claim 1 , wherein the layer is one of a monocrystalline layer or a polycrystalline layer. 
     
     
       11. The method of  claim 1 , further comprising:
 patterning the first region to define a first transistor gate electrode having said first thickness; 
 patterning the second region to define a second transistor electrode having said second thickness. 
 
     
     
       12. The method of  claim 11 , further comprising:
 depositing a metal layer on the first transistor gate electrode and the second transistor gate electrode; 
 performing an annealing so to transform of the first transistor gate electrode into a first silicided gate electrode and transform the second transistor gate electrode into a second silicided gate electrode. 
 
     
     
       13. The method of  claim 12 , wherein the first silicided gate electrode has a metal-poor silicide phase and the second silicided gate electrode has a metal-rich silicide phase. 
     
     
       14. The method of  claim 12 , wherein performing the annealing comprises:
 performing a first annealing at a first annealing temperature and first annealing time suitable for forming a fully-silicided metal-rich silicide phase for the second silicided gate electrode and forming a partially-silicided first transistor gate electrode; and 
 performing a second annealing at a second annealing temperature and second annealing time suitable for forming a fully-silicided metal-poor silicide phase for the first transistor gate electrode. 
 
     
     
       15. The method of  claim 11 , further comprising providing lateral spacers on either side of the first and second transistor gate electrodes. 
     
     
       16. The method of  claim 15 , further comprising depositing silicon on the substrate adjacent the lateral spacers to provide a source and a drain for each of the first and second transistor gate electrodes. 
     
     
       17. A method, comprising:
 defining on a surface of a layer on a semiconductor substrate a first surface region and a second surface region, the layer comprising silicon or silicon-germanium; 
 implanting a Boron dopant into the second surface region but not the first surface region; 
 selectively passivating the semiconductor substrate such that the Boron doped second surface region is not passivated while the non-Boron doped first surface region is passivated; 
 performing a deposition on the surface of the semiconductor substrate in the absence of a mask which causes selective growth of silicon or silicon-germanium over the passivated non-Boron doped first surface region to form a first region having a first thickness and wherein growth is suppressed over the non-passivated Boron doped second surface region to form a second region having a second thickness less than the first thickness. 
 
     
     
       18. The method of  claim 17 , wherein selectively passivating comprises baking the semiconductor substrate in a passivating H 2  ambient atmosphere at a temperature below or equal to 800° Centigrade. 
     
     
       19. The method of  claim 17 , wherein second surface region doped with Boron has a Boron dopant concentration of at least 1×10 19  cm −3 . 
     
     
       20. The method of  claim 17 , further comprising:
 patterning the first region to define a first transistor gate electrode having said first thickness; 
 patterning the second region to define a second transistor gate electrode having said second thickness. 
 
     
     
       21. The method of  claim 20 , further comprising:
 depositing a metal layer on the first transistor gate electrode and the second transistor gate electrode; 
 performing an annealing so to transform of the first transistor gate electrode into a first silicided gate electrode and transform the second transistor gate electrode into a second silicided gate electrode. 
 
     
     
       22. The method of  claim 21 , wherein the first silicided gate electrode has a metal-poor silicide phase and the second silicided gate electrode has a metal-rich silicide phase. 
     
     
       23. The method of  claim 21 , wherein performing the annealing comprises:
 performing a first annealing at a first annealing temperature and first annealing time suitable for forming a fully-silicided metal-rich silicide phase for the second silicided gate electrode and forming a partially-silicided first transistor gate electrode; and 
 performing a second annealing at a second annealing temperature and second annealing time suitable for forming a fully-silicided metal-poor silicide phase for the first transistor gate electrode. 
 
     
     
       24. A method, comprising:
 preparing a semiconductor substrate having a layer with a first region and a second region; 
 implanting Boron at a concentration of at least 1×10 19  cm −3  in only the second region and not the first region; 
 selectively passivating the semiconductor substrate such that the Boron doped second region is not passivated while the non-Boron doped first region is passivated; 
 depositing a silicon-based overlayer after implanting and passivating, and without masking, said silicon-based overlayer provided on the non-Boron doped first region and not provided on the Boron doped second region; 
 siliciding both the first region and the second region to form a first metal silicide phase in the first region and a second metal silicide phase in the second region, wherein the first metal silicide phase has a lower relative metal content than the second metal silicide phase. 
 
     
     
       25. The method of  claim 24 , wherein siliciding comprises:
 depositing a metal layer having a same thickness over each of the first and second regions; 
 annealing at a first temperature and first time span to form a fully-silicided phase for the second region and a partially-silicided phase for the first region; and 
 annealing at a second temperature and a second time span to convert the partially-silicided phase for the first region into a fully-silicided phase for the first region. 
 
     
     
       26. The method of  claim 24 , further comprising patterning the first region and the second region to define first and second transistor gate electrodes, respectively, said first and second transistor gate electrodes being fully silicided by said step of siliciding, and said first and second transistor gate electrodes having different silicide phases. 
     
     
       27. The method of  claim 26 , further comprising depositing a silicon-based material for source and drain structures on either side of each of the first and second transistor gate electrodes. 
     
     
       28. A method, comprising:
 preparing a layer on a semiconductor substrate to have a first region and a second region, the layer comprising silicon or silicon-germanium; 
 implanting a Boron dopant in the second region to a concentration of at least 1×10 19  cm −3 , thereby providing on the layer both an implanted surface and an unimplanted surface; 
 passivating the semiconductor substrate at temperature which provides an unpassivated surface in the second region and a passivated surface in the first region, where said unpassivated surface suppresses further silicon or silicon-germanium deposition on said surface in the second regions while the passivated surface in the first region allows for further silicon or silicon-germanium deposition on the semiconductor substrate; and 
 performing a selective deposition of silicon or silicon-germanium on the semiconductor substrate over the first region but not over the second region. 
 
     
     
       29. The method of  claim 28 , wherein passivating comprises performing a hydrogen passivation at an ambient atmosphere and a temperature less than or equal to 800° Centigrade. 
     
     
       30. The method of  claim 28 , further comprising cleaning the semiconductor substrate with hydrofluoridic acid after implanting. 
     
     
       31. The method of  claim 28 , further comprising siliciding the silicon or silicon-germanium material of the layer on the semiconductor substrate to form a first silicide phase in the first region and a second silicide phase in the second region. 
     
     
       32. The method of  claim 31 , wherein the first silicide phase is a metal-poor silicide phase and the second silicide phase is a metal-rich silicide phase. 
     
     
       33. The method of  claim 32 , wherein the first region is patterned to form a first transistor gate electrode, and the metal-poor silicide phase defines a first fully silicided transistor gate electrode, and wherein the second region is patterned to form a second transistor gate electrode, and the metal-rich silicide phase defines a second fully silicided transistor gate electrode. 
     
     
       34. The method of  claim 33 , wherein the first fully silicided transistor gate electrode is defined for an nMOS transistor and the second fully silicided transistor gate electrode is defined for a pMOS transistor.