Method of gain calibration of an ADC stage and an ADC stage

Abstract

A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.

The invention claimed is: 
     
       1. A method of calibrating an analog to digital converter system, comprising:
 receiving an input analog signal; 
 converting the input analog signal into an m-bit digital signal using an analog to digital converter; 
 generating a calibration signal using a random number generator, the calibration signal being positive, null, or negative based on a state of a digital signal generated by the random number generator; 
 adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal; 
 converting the adjusted m-bit digital signal into an adjusted partial analog signal using a digital to analogue converter; 
 subtracting the partial analog signal from the input analog signal, to produce a residual analog signal; and 
 amplifying the residual analog signal. 
 
     
     
       2. A method as claimed in  claim 1 , wherein the state of the digital signal comprises any one of three states including a negative state, zero, and a positive state. 
     
     
       3. The method as claimed in  claim 2 , wherein the negative state is −1, and the positive state is +1. 
     
     
       4. The method as claimed in  claim 2 , wherein, when the input analog signal lies within a lowest sub-range, the random generator is constrained to be the negative state and 0. 
     
     
       5. The method as claimed in  claim 2 , wherein, when the input analog signal lies within a highest sub-range, the random generator is constrained to be zero and the positive state. 
     
     
       6. A stage of an analog-to-digital converter (ADC), the stage of the ADC calibrating the ADC according to the method of  claim 1 . 
     
     
       7. The stage of an ADC according to  claim 6 , wherein the stage is a pipeline stage. 
     
     
       8. A method of calibrating an analog to digital converter system, comprising:
 receiving an input analog signal; 
 converting the input analog signal into an m-bit digital signal using an analog to digital converter; 
 generating a calibration signal using a random number generator, wherein the random number generator generates a digital signal having any one of three states including a negative state, zero, and a positive state, the calibration signal being positive, null, or negative based on the state of the digital signal generated by the random number generator, and the random number generator constrained to be two of the three states based on the input analog signal; 
 adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal; 
 converting the adjusted m-bit digital signal into an adjusted partial analog signal using a digital to analogue converter; 
 subtracting the partial analog signal from the input analog signal, to produce a residual analog signal; and 
 amplifying the residual analog signal. 
 
     
     
       9. The method as claimed in  claim 8 , wherein the negative state is −1, and the positive state is +1. 
     
     
       10. A stage of an analog-to-digital converter (ADC), the stage of the ADC calibrating the ADC according to the method of  claim 8 . 
     
     
       11. The stage of an ADC according to  claim 10 , wherein the stage is a pipeline stage.