Shorted test structure

Abstract

A shorted test structure and methods for making it are disclosed. A conductive layer is applied over a first surface of a blank substrate. The blank substrate has a plurality of conductive vias that electrically connect solder lands on the first surface of the blank substrate to corresponding solder contacts on a second surface of the substrate. The conductive layer electrically couples the solder lands.

What is claimed is: 
     
       1. A method for making a shorted test structure, comprising:
 applying a conductive layer over a first surface of a blank substrate, wherein the blank substrate has a plurality of conductive vias that electrically connect solder lands on the first surface of the blank substrate to corresponding solder contacts on a second surface of the substrate, and the conductive layer electrically couples the solder lands; 
 wherein the solder lands are arranged in an array and the conductive layer electrically connects each solder land in the array to all other solder lands in the array, and areas of the first surface between adjacent ones of the solder lands are completely covered with the conductive layer; and 
 attaching a lid to the first surface of the blank substrate, wherein a void is created between the conductive layer and a surface of the lid that faces the conductive layer. 
 
     
     
       2. The method of  claim 1 , wherein the applying includes applying conductive paint with a brush. 
     
     
       3. The method of  claim 1 , wherein the applying includes spraying conductive paint. 
     
     
       4. The method of  claim 1 , wherein the applying includes spreading two or more coats of conductive paint. 
     
     
       5. The method of  claim 1 , wherein the conductive layer includes solder. 
     
     
       6. The method of  claim 1 , wherein the conductive layer includes metal tape. 
     
     
       7. The method of  claim 1 , wherein the substrate is an interposing substrate. 
     
     
       8. The method of  claim 1 , wherein the substrate is a carrier substrate. 
     
     
       9. The method of  claim 1 , further comprising attaching a package lid to the substrate, the package lid covering the conductive layer. 
     
     
       10. The method of  claim 1 , wherein the conductive layer is a metal paint and further comprising curing the painted substrate for approximately 10 minutes at 125° C. 
     
     
       11. A method for verifying short-circuit test functions of a test apparatus, comprising:
 applying a conductive layer over a first surface of a blank substrate, wherein the blank substrate has a plurality of conductive vias that connect solder lands on the first surface of the blank substrate to corresponding solder contacts on a second surface of the substrate, and the conductive layer electrically couples the solder lands; 
 wherein the solder lands are arranged in an array and the conductive layer electrically connects each solder land in the array to all other solder lands in the array, and areas of the first surface between adjacent ones of the solder lands are completely covered with the conductive layer; 
 attaching a lid to the first surface of the blank substrate, wherein a void is created between the conductive layer and a surface of the lid that faces the conductive layer; 
 coupling the substrate having the conductive layer to a test apparatus via the solder balls; and 
 testing for short circuits on the substrate on the test apparatus. 
 
     
     
       12. The method of  claim 11 , wherein the applying includes applying conductive paint with a brush. 
     
     
       13. The method of  claim 11 , wherein the applying includes spraying conductive paint. 
     
     
       14. The method of  claim 11 , wherein the applying includes spreading two or more coats of conductive paint. 
     
     
       15. The method of  claim 11 , wherein the conductive layer includes solder. 
     
     
       16. The method of  claim 11 , wherein the conductive layer includes metal tape. 
     
     
       17. A test structure, comprising:
 a blank substrate having a plurality of conductive vias that connect solder lands on a first surface of the blank substrate to corresponding solder contacts on a second surface of the substrate; 
 wherein the solder lands are arranged in an array; 
 a conductive layer on the first surface of the blank substrate, wherein the conductive layer electrically connects each solder land in the array to all other solder lands in the array, and areas of the first surface between adjacent ones of the solder lands are completely covered with the conductive layer; and 
 a lid attached to the first surface of the blank substrate, wherein a void is present between the conductive layer and a surface of the lid that faces the conductive layer. 
 
     
     
       18. The test structure of  claim 17 , wherein the conductive layer includes conductive paint. 
     
     
       19. The test structure of  claim 17 , wherein the conductive layer includes solder. 
     
     
       20. The test structure of  claim 17 , wherein the conductive layer includes metal tape.