Package unit and stacking structure thereof

Abstract

A package unit and a stacking structure thereof are provided. The package unit includes a substrate, a first patterned circuit layer, a first conductive pillar, a semiconductor element, an insulation layer, a second conductive pillar, a third conductive pillar, a second patterned circuit layer and a conductive bump. The first patterned circuit layer is disposed on a surface of the substrate. The first conductive pillar is deposited through the substrate. The semiconductor element is disposed on the substrate. The insulation layer covers the semiconductor element and the substrate. The second conductive pillar is deposited through the insulation layer. The third conductive pillar is deposited through the insulation layer. The second patterned circuit layer is disposed on the insulation layer. The conductive bump is disposed on the second patterned metal layer.

What is claimed is: 
     
       1. A package unit, comprising:
 a substrate; 
 a first patterned circuit layer disposed on a surface of the substrate; 
 a first conductive pillar deposited through the substrate and electrically connected to the first patterned circuit layer; 
 an isolation layer formed on the first patterned circuit layer, wherein the isolation layer has an opening exposing a part of the first patterned circuit to form a pad; 
 a semiconductor element disposed on the substrate, wherein the semiconductor element comprises at least one chip; 
 an insulation layer covering the semiconductor element and the substrate; 
 a second conductive pillar deposited through the insulation layer and electrically connected to the first conductive pillar; 
 a third conductive pillar deposited through the insulation layer and electrically connected to the semiconductor element; 
 a second patterned circuit layer disposed on the insulation layer and electrically connected to the second and the third conductive pillars; and 
 a conductive bump disposed on the second patterned metal layer. 
 
     
     
       2. The package unit according to  claim 1 , further comprising:
 an inter-metallic compound layer disposed between the first conductive pillar and the second conductive pillar, wherein the first conductive pillar and the second conductive pillar both contain Cu, and the inter-metallic compound layer contains a Sn—Cu compound. 
 
     
     
       3. The package unit according to  claim 1 , wherein the inter-metallic compound layer is formed by plating, electroless plating or inject printing. 
     
     
       4. The package unit according to  claim 1 , wherein the first conductive pillar and the second conductive pillar surround the semiconductor element. 
     
     
       5. The package unit according to  claim 1 , wherein the third conductive pillar is disposed on the semiconductor element. 
     
     
       6. The package unit according to  claim 1 , wherein the length of the second conductive pillar is larger than the thickness of the semiconductor element. 
     
     
       7. The package unit according to  claim 1 , wherein the thickness of the insulation layer is larger than that of the semiconductor element. 
     
     
       8. The package unit according to  claim 1 , wherein the semiconductor element is disposed on one surface of the substrate. 
     
     
       9. The package unit according to  claim 1 , wherein the insulation layer covers a top surface and a lateral side of the semiconductor element. 
     
     
       10. A stacking structure of a package unit, comprising:
 at least two package units each comprising: 
 a substrate; 
 a first patterned circuit layer disposed on a surface of the substrate; 
 a first conductive pillar deposited through the substrate and electrically connected to the first patterned circuit layer; 
 an isolation layer formed on the first patterned circuit layer, wherein the isolation layer has an opening exposing a part of the first patterned circuit to form a pad; 
 a semiconductor element disposed on the substrate, wherein the semiconductor element comprises at least one chip; 
 an insulation layer covering the semiconductor element and the substrate; 
 a second conductive pillar deposited through the insulation layer and electrically connected to the first conductive pillar; 
 a third conductive pillar deposited through the insulation layer and electrically connected to the semiconductor element; 
 a second patterned circuit layer disposed on the insulation layer and electrically connected to the second and the third conductive pillars; and 
 a conductive bump disposed on the second patterned metal layer; 
 wherein one of the first patterned circuits of the package units is disposed on one of the conductive bumps of the other package units.