Reference frequency generation circuit, semiconductor integrated circuit, and electronic device

Abstract

An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

What is claimed is: 
     
       1. A reference frequency generation circuit which generates a reference clock, the circuit comprising:
 an oscillator circuit configured to alternately perform, in response to a transition of a signal level of the reference clock, an operation to increase a signal level of a first oscillation signal and reduce a signal level of a second oscillation signal, and an operation to increase the signal level of the second oscillation signal and reduce the signal level of the first oscillation signal; 
 an oscillation control circuit configured to cause, when detecting that the signal level of the first oscillation signal has reached a comparison voltage, the signal level of the reference clock to transition to a first logic level, and cause, when detecting that the signal level of the second oscillation signal has reached the comparison voltage, the signal level of the reference clock to transition to a second logic level; 
 a reference control circuit configured to increase or reduce the comparison voltage such that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced; and 
 a reference voltage control circuit configured to increase or reduce the reference voltage according to a frequency difference between a basis clock having a predetermined basis frequency and the reference clock. 
 
     
     
       2. The circuit of  claim 1 , wherein
 the reference voltage control circuit is switchable between a frequency correction mode and a constant frequency mode, 
 in the frequency correction mode, the reference voltage control circuit increases or reduces the reference voltage according to the frequency difference between the basis clock and the reference clock, and 
 in the constant frequency mode, the reference voltage control circuit maintains the reference voltage regardless of the frequency difference between the basis clock and the reference clock. 
 
     
     
       3. The circuit of  claim 2 , wherein
 the reference voltage control circuit includes: 
 a frequency comparator configured to count the number of transitions of the basis clock and the number of transitions of the reference clock in a predetermined period and output, as a frequency difference value, a difference in the number of transitions between the basis clock and the reference clock in the frequency correction mode, and to maintain the frequency difference value in the constant frequency mode; 
 a digital controller configured to increase or reduce, according to the frequency difference value, a control value corresponding to a voltage level of the reference voltage; and 
 a digital-to-analog converter configured to convert the control value into the reference voltage. 
 
     
     
       4. The circuit of  claim 1 , wherein
 the reference voltage control circuit includes: 
 a phase frequency comparator configured to detect a phase difference and a frequency difference between the basis clock and the reference clock, and to output a phase difference value and a frequency difference value respectively corresponding to the phase difference and the frequency difference; 
 a digital controller configured to increase or reduce, according to the phase difference value and the frequency difference value, a control value corresponding to a voltage level of the reference voltage; 
 a ΔΣ modulator configured to perform ΔΣ modulation on the control value obtained by the digital controller; 
 a digital-to-analog converter configured to convert the control value processes by the ΔΣ modulator into the reference voltage; and 
 a low-pass filter configured to attenuate high-frequency components of the reference voltage obtained by the digital-to-analog converter. 
 
     
     
       5. The circuit of  claim 3 , wherein
 the digital-to-analog converter includes: 
 a resistance divider configured to generate a plurality of different analog voltages by resistance division between a first voltage and a second voltage which are different from each other; and 
 a selector configured to select, as the reference voltage, one of the analog voltages generated by the resistance divider according to the control value provided to the digital-to-analog converter. 
 
     
     
       6. The circuit of  claim 1 , wherein
 the reference voltage control circuit includes: 
 a frequency divider configured to divide a frequency of the reference clock to output a divided clock; 
 a phase frequency comparator configured to detect a phase difference and a frequency difference between the basis clock and the divided clock, and to output a charge signal or a discharge signal according to the phase difference and the frequency difference; 
 a charge pump configured to output, as an output current, one of a charge current for increasing the reference voltage or a discharge current for reducing the reference voltage, in response to the charge signal or the discharge signal; and 
 a low-pass filter configured to convert the output current from the charge pump into the reference voltage. 
 
     
     
       7. The circuit of  claim 1 , wherein
 the reference voltage control circuit includes: 
 a frequency divider configured to divide a frequency of the reference clock to output a divided clock; 
 a phase frequency comparator configured to detect a phase difference and a frequency difference between the basis clock and the divided clock, and to output an output current according to the phase difference and the frequency difference; and 
 a low-pass filter configured to convert the output current from the phase frequency comparator into the reference voltage. 
 
     
     
       8. The circuit of  claim 1 , wherein
 the basis clock is supplied to the reference voltage control circuit through a radio path. 
 
     
     
       9. The circuit of  claim 2 , wherein
 a period during which the reference voltage control circuit is in the frequency correction mode is set in an inspection period during which the reference frequency generation circuit or a semiconductor integrated circuit including the reference frequency generation circuit is subjected to an inspection before shipment from a factory. 
 
     
     
       10. The circuit of  claim 2 , wherein
 a period during which the reference voltage control circuit is in the frequency correction mode is set in a period during which an electronic device including the reference frequency generation circuit is not in operation. 
 
     
     
       11. The circuit of  claim 2 , wherein
 a period during which the reference voltage control circuit is in the frequency correction mode is set after selection of a channel by a receiver including the reference frequency generation circuit. 
 
     
     
       12. The circuit of  claim 2 , wherein
 a period during which the reference voltage control circuit is in the frequency correction mode is set after selection of a musical piece or immediately before playing back of the musical piece by an audio playback device including the reference frequency generation circuit. 
 
     
     
       13. The circuit of  claim 2 , wherein
 a period during which the reference voltage control circuit is in the frequency correction mode is set after selection of a moving image or immediately before playing back of the moving image by an image playback device including the reference frequency generation circuit. 
 
     
     
       14. A semiconductor integrated circuit, comprising:
 the reference frequency generation circuit of  claim 1 ; and 
 a CPU configured to operate in synchronization with the reference clock from the reference frequency generation circuit. 
 
     
     
       15. An electronic device, comprising:
 the semiconductor integrated circuit of  claim 14 . 
 
     
     
       16. The circuit of  claim 4 , wherein
 the digital-to-analog converter includes: 
 a resistance divider configured to generate a plurality of different analog voltages by resistance division between a first voltage and a second voltage which are different from each other; and 
 a selector configured to select, as the reference voltage, one of the analog voltages generated by the resistance divider according to the control value provided to the digital-to-analog converter.