Measurement method and apparatus for ADC calibration

Abstract

An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors.

We claim: 
     
       1. An analog-to-digital converter (ADC) for converting an input signal to a multi-bit digital code, comprising:
 a converter element array comprising:
 for a first range of least significant bits of the digital code, a plurality of converter elements, at least one converter element provided for each bit in the first range, 
 for a second range of most significant bits of the digital code, a plurality of converter elements provided for each bit in the second range, and 
 a switch control of the converter element array individually switching each of the converter elements in the second range at least once between two reference potentials; and 
 
 a comparator coupled to the converter element array capable of generating digital output codes from output signals at converter elements in the first range corresponding to each of the two reference potentials individually applied to the converter elements in the second range, 
 wherein the switch control individually switches each of the converter elements between the two reference potentials to individually calibrate each of the converter elements and 
 wherein each respective generated digital output code is a calibration value for a respective converter element in the second range that is subsequently used to correct an output of the respective converter element. 
 
     
     
       2. The ADC of  claim 1 , wherein, the switch control is capable of individually switching each of the converter elements in the second range during a first mode of operation and is capable of switching in unison those converter elements provided for a respective bit in the second range during a second mode of operation. 
     
     
       3. The ADC of  claim 1 , wherein the converter elements are capacitors and the converter element array is a capacitive digital-to-analog (DAC) array. 
     
     
       4. The ADC of  claim 3 , wherein the capacitive DAC array is binary weighted, a pair of capacitors are provided for each bit in the second range, a single capacitor is provided for each bit in the first range, and each capacitor provided for a lowest bit in the second range has a capacitance generally equal to that of the single capacitor provided for a highest bit in the first range. 
     
     
       5. The ADC of  claim 1 , further comprising a logic circuit coupled to the comparator, wherein the ADC operates in a calibration mode in which:
 the logic circuit calculates a difference between the digital output codes corresponding to each of the two reference potentials to calibrate the converter element being individually switched by the switch control. 
 
     
     
       6. An analog-to-digital converter (ADC) comprising:
 a plurality of capacitors provided for a first bit in the ADC; 
 at least one capacitor provided for each lesser significant bit in the ADC than the first bit and coupled to the plurality of first bit capacitors; and 
 a switching arrangement individually switching each of the first bit capacitors at least once between a plurality of potentials, 
 wherein a capacitance of each first bit capacitor is less than a total capacitance of the lesser significant bit capacitor(s), 
 wherein the switching arrangement individually switches each of the first bit capacitors between the potentials to generate a calibration value for each respective first bit capacitor that is subsequently used to correct an output of the ADC. 
 
     
     
       7. The ADC of  claim 6 , wherein the switching arrangement is configured to individually switch each of the first bit capacitors between the plurality of potentials during a first mode of operation and is configured to switch the plurality of first bit capacitors in unison during a second mode of operation. 
     
     
       8. The ADC of  claim 6 , wherein the plurality of potentials include a ground potential and a reference potential. 
     
     
       9. The ADC of  claim 6 , further comprising a digital code generating arrangement to generate a digital code from a voltage change at the lesser significant bit capacitor(s) responsive to the switching arrangement switching one of the first bit capacitors between the potentials. 
     
     
       10. The ADC of  claim 6 , further comprising a circuitry arrangement to prevent a first bit capacitor that was not switched between potentials from affecting the voltage change at the lesser significant capacitor(s). 
     
     
       11. An analog-to-digital converter (ADC) comprising:
 a plurality of converter elements provided for a plurality of less significant bits in the ADC; 
 a plurality of converter elements provided for each more significant bit in the ADC, the more significant bit converter elements coupled to the less significant bit converter elements; 
 a switchably enabled selector individually toggling each of the more significant bit converter elements at least once between a reference signal and a ground and decoupling those non-toggled converter elements at a same or more significant bit than the converter element being individually toggled; 
 a comparator to generate digital output codes from a change in electric charge at the less significant converter elements responsive to the toggling; and 
 a logic circuit to store and compare the generated digital output codes, 
 wherein the switchably enabled selector individually toggles each of the more significant bit converter elements between the reference signal and the ground to individually calibrate each of the more significant bit converter elements and 
 wherein the generated digital output codes are calibration values for respective more significant bit converter elements that are subsequently used to correct an output of the respective converter elements. 
 
     
     
       12. The ADC of  claim 11 , wherein, the switchably enabled selector is capable of individually toggling each of the more significant bit converter elements between the reference signal and the ground during a first mode of operation and is capable of switching in unison those converter elements provided for a respective more significant bit during a second mode of operation. 
     
     
       13. A method for calibrating a converter element in an analog-to-digital converter (ADC) comprising:
 at a more significant bit in the ADC:
 switching a first of a plurality of converter elements provided for the more significant bit to a first reference potential; 
 identifying a first voltage change at an output of converter elements provided for less significant bits in the ADC coupled to the first converter element; 
 switching the first converter element to a second reference potential; 
 identifying a second voltage change at the output of the converter elements provided for less significant bits; 
 comparing the first voltage change to the second voltage change; 
 identifying a calibration value of the first converter element based on the comparing, wherein the calibration value is subsequently used correct an output of the respective converter element; and 
 repeating the method for each of the plurality of converter elements provided for the more significant bit. 
 
 
     
     
       14. The method of  claim 13 , wherein the first and second voltage changes are identified from ADC output codes corresponding to each of the voltage changes and the comparing the first voltage change to the second voltage change includes comparing the generated ADC output codes. 
     
     
       15. The method of  claim 13 , further comprising calibrating the first converter element according to the result of the comparing. 
     
     
       16. The method of  claim 13 , further comprising storing a result of the comparing as a calibration of the first converter element. 
     
     
       17. The method of  claim 13 , wherein, in a differential successive approximation register ADC having a pair of complementary signal lines, the converter elements are capacitors, the first and second voltage changes are identified at the output of the converter elements provided for less significant bits in both of the complementary signal lines, and the converter elements provided for less significant bits in both of the complementary signal lines are coupled to the first converter element provided for the more significant bit. 
     
     
       18. The method of  claim 13 , wherein the second reference potential is a ground potential. 
     
     
       19. The method of  claim 13 , wherein the converter elements are capacitors and the first converter element has a capacitance equivalent to one of the lower order bit converter elements. 
     
     
       20. The method of  claim 13 , further comprising iteratively repeating the method substituting for the first converter element a remaining unswitched converter element from a plurality of converter elements provided for a plurality of more significant bits. 
     
     
       21. The method of  claim 20 , further comprising:
 at runtime, after substituting all remaining unswitched converter elements provided for the plurality of more significant bits,
 calibrating each of the switched converter elements according to a result of the comparing the first voltage change to the second voltage change for each of the switched converter elements; and 
 adjusting a ADC output code at the more significant bits according to the calibration. 
 
 
     
     
       22. The method of  claim 21 , further comprising, switching in unison the plurality of converter elements provided for at least one of the more significant bits during a subsequent mode of operation after calibrating each of the switched converter elements. 
     
     
       23. A pipeline analog-digital converter (ADC) comprising:
 a backend ADC coupled to a first capacitor and an output of an amplifier; 
 a plurality of second capacitors coupled to the first capacitor and an input of the amplifier; 
 a switching arrangement coupled to a plurality of second capacitors and individually switching each of the second capacitors at least once between a plurality of potentials, 
 wherein the switching arrangement individually switches each of the second capacitors between the potentials to generate a calibration value for each respective second capacitor that is subsequently used to correct an output of the second capacitor. 
 
     
     
       24. The pipeline ADC of  claim 23 , wherein, the switching arrangement individually switches each of the second capacitors between a plurality of potentials during a first mode of operation and switches the second capacitors in unison during a second mode of operation. 
     
     
       25. The pipeline ADC of  claim 23 , wherein the switching arrangement is configured to open circuit those second capacitors that are not being switched. 
     
     
       26. The pipeline ADC of  claim 23 , wherein each of the second capacitors has a capacitance less than that of the first capacitor.