Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit

Abstract

A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

What is claimed is: 
     
       1. A priority circuit that is connected to a reservation station that includes a plurality of entries therein and supplies a decoded instruction decoded by an instruction decoder to be operated and executable information outputted from the instruction decoder indicating that a corresponding decoded instruction can be executed only by a specific arithmetic unit of a plurality of arithmetic units or the corresponding decoded instruction can be executed not only by the specific arithmetic unit but by an arithmetic unit different from the specific arithmetic unit of the plurality of arithmetic units, the decoded instruction and corresponding executable information are held in each of the plurality of entries, and the plurality of arithmetic units each have an instruction queue storing the decoded instruction supplied from the reservation station and each execute a different operation based on the decoded instruction stored in the instruction queue, the priority circuit comprising:
 a dispatching unit that dispatches the decoded instruction to the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed only by the specific arithmetic unit and dispatches the decoded instruction to an arithmetic unit different from the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed not only by the specific arithmetic unit but by the arithmetic unit different from the specific arithmetic unit and of which an instruction queue is vacant. 
 
     
     
       2. The priority circuit according to  claim 1 , wherein
 the dispatching unit dispatches the decoded instruction to an arithmetic unit different from the specific arithmetic unit when corresponding dispatch inhibition information indicates that the decoded instruction cannot be dispatched to a specific arithmetic unit and of which a queue is vacant. 
 
     
     
       3. A processor comprising:
 a reservation station that includes a plurality of entries therein and supplies a decoded instruction to be operated and executable information; 
 a plurality of arithmetic units that each have an instruction queue storing the decoded instruction supplied from the reservation station and each execute a different operation based on the decoded instruction stored in the instruction queue; 
 an instruction decoder that decodes and outputs the decoded instruction and the executable information indicating that an instruction can be executed only by a specific arithmetic unit or the corresponding decoded instruction can be executed not only by the specific arithmetic unit but by an arithmetic unit different from the specific arithmetic unit of the plurality of arithmetic units; and 
 a priority circuit that dispatches the decoded instruction to the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed only by the specific arithmetic unit and dispatches the decoded instruction to an arithmetic unit that is different from the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed not only by the specific arithmetic unit but by the arithmetic unit different from the specific arithmetic unit and of which an instruction queue is vacant. 
 
     
     
       4. The processor according to  claim 3 , wherein
 the priority circuit dispatches the decoded instruction to an arithmetic unit that is different from the specific arithmetic unit when corresponding dispatch inhibition information indicates that the decoded instruction cannot be dispatched to a specific arithmetic unit and of which a queue is vacant. 
 
     
     
       5. A processing method of a processor that includes a reservation station that includes a plurality of entries therein and supplies a decoded instruction to be operated and executable information and a plurality of arithmetic units that each have an instruction queue and each execute a different operation, the processing method comprising:
 outputting a decoded instruction and the executable information indicating that a corresponding decoded instruction can be executed only by a specific arithmetic unit of a plurality of arithmetic units or the corresponding decoded instruction can be executed not only by the specific arithmetic unit but by an arithmetic unit different from the specific arithmetic unit of the plurality of arithmetic units; 
 dispatching the decoded instruction to the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed only by the specific arithmetic unit; 
 dispatching the decoded instruction to an arithmetic unit that is different from the specific arithmetic unit when the corresponding executable information indicates that the decoded instruction can be executed not only by the specific arithmetic unit but by the arithmetic unit different from the specific arithmetic unit and of which an instruction queue is vacant. 
 
     
     
       6. The processing method according to  claim 5 , wherein
 the dispatching dispatches the decoded instruction to an arithmetic unit that is different from the specific arithmetic unit when corresponding dispatch inhibition information indicates that the decoded instruction cannot be dispatched to a specific arithmetic unit and of which a queue is vacant.