Low dropout regulator with multiplexed power supplies

Abstract

Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a multiplexer to commonly control the back-gates of multiple power transistors within the LDO. By doing this, the area overhead that would normally be present with these switches (of the multiplexer) can be dramatically reduced without sacrificing performance.

The invention claimed is: 
     
       1. An apparatus comprising:
 a plurality of power supply terminals; 
 an output terminal; 
 a supply node; 
 a plurality of switches, wherein each switch is directly coupled to at least one of the power supply terminals, and wherein each switch is directly coupled to the supply node, and wherein each switch is controlled by at least one of a plurality of control signals; 
 a plurality of power transistors, wherein each power transistor has a body electrode, a first passive electrode, a second passive electrode, and a control electrode, and wherein each power transistor is directly coupled to the supply node at its body electrode, and wherein the first passive electrode of each power transistor is directly coupled to at least one of the power supply terminals, and wherein the second passive electrode of each power transistor is directly coupled to the output terminal; 
 a plurality of buffers, wherein each buffer is directly coupled to the control electrode of at least one of the power transistors; and 
 an amplifier that is directly coupled to each buffer. 
 
     
     
       2. The apparatus of  claim 1 , wherein each switch further comprises a pair of back-to-back PMOS transistors. 
     
     
       3. The apparatus of  claim 2 , wherein each of the power transistors further comprises a PMOS transistor. 
     
     
       4. An apparatus comprising:
 a first power supply terminal; 
 a second power supply terminal; 
 an output terminal; 
 a supply node; 
 a first switch that is coupled between the first power supply terminal and the supply node; 
 a second switch that is coupled between the second power supply terminal and the supply node; 
 a first power transistor having a body electrode, a first passive electrode, a second passive electrode, and a control electrode, wherein the supply node is coupled to the first power transistor at its body electrode, and wherein the first power transistor is coupled to the first power supply terminal at its first passive electrode, and wherein the first power transistor is coupled to the output terminal at its second passive electrode; 
 a second power transistor having a body electrode, a first passive electrode, a second passive electrode, and a control electrode, wherein the supply node is coupled to the second power transistor at its body electrode, and wherein the second power transistor is coupled to the second power supply terminal at its first passive electrode, and wherein the second power transistor is coupled to the output terminal at its second passive electrode; 
 a first buffer that is coupled to the first power transistor at its control electrode; 
 a second buffer that is coupled to the first power transistor at its control electrode; and 
 an amplifier that is coupled to each buffer. 
 
     
     
       5. The apparatus of  claim 4 , wherein the first and second power transistors further comprises first and second PMOS transistors, respectively. 
     
     
       6. The apparatus of  claim 5 , wherein the first switch further comprises:
 a third PMOS transistor that is coupled to the first power supply terminal at its drain, wherein the body and source of the third PMOS transistor are coupled together; and 
 a fourth PMOS transistor that is coupled to the source of the third PMOS transistor at its body and source and that is coupled to the supply node at its drain. 
 
     
     
       7. The apparatus of  claim 6 , wherein the second switch further comprises:
 a fifth PMOS transistor that is coupled to the second power supply terminal at its drain, wherein the body and source of the fifth PMOS transistor are coupled together; and 
 a sixth PMOS transistor that is coupled to the source of the fifth PMOS transistor at its body and source and that is coupled to the supply node at its drain.