Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same

Abstract

An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

That which is claimed is: 
     
       1. A non-volatile memory device, comprising:
 a NAND-type string of non-volatile memory cells including at least a first vertically-stacked array of charge trap memory cells on a semiconductor substrate, a string select transistor on a first side of the first vertically-stacked array of charge trap memory cells and a ground select transistor on a second side of the first vertically stacked array of charge trap memory cells, said first vertically-stacked array of charge trap memory cells comprising a semiconductor layer covering first and second opposing sidewalls thereof, said semiconductor layer electrically connected to a first source/drain terminal of the string select transistor; 
 wherein said string select and ground select transistors are MOSFETs having respective channel regions in the semiconductor substrate; and 
 wherein said semiconductor layer contains channel regions of the first vertically-stacked array of charge trap memory cells therein. 
 
     
     
       2. The device of  claim 1 , wherein said semiconductor layer is electrically connected to a first source/drain terminal of the ground select transistor. 
     
     
       3. The device of  claim 1 , wherein the semiconductor substrate comprises an electrically insulating layer therein; and wherein said first vertically-stacked array of charge trap memory cells is disposed on the electrically insulating layer. 
     
     
       4. The device of  claim 3 , wherein said NAND-type string of non-volatile memory cells comprises a second vertically-stacked array of charge trap memory cells on the electrically insulating layer; and wherein the semiconductor layer covers first and second opposing sidewalls of the second vertically-stacked array of charge trap memory cells. 
     
     
       5. The device of  claim 2 , further comprising:
 a bit line electrically coupled to a second source/drain terminal of the string select transistor; and 
 a ground select line electrically coupled to a second source/drain terminal of the ground select transistor. 
 
     
     
       6. The device of  claim 1 , wherein all of the cells in the first vertically-stacked array of charge trap memory cells are configured to store nonvolatile data when programmed. 
     
     
       7. A semiconductor memory device comprising:
 a ground selection structure and a string selection structure being apart from each other; 
 at least one memory structure between the ground and string selection structures, the memory structure comprising a plurality of word lines stacked sequentially; 
 at least one semiconductor pattern crossing the word lines to connect the ground selection structure to the string selection structure and covering a top surface and sidewall of the memory structure; and 
 a substrate disposed under the ground and string selection structures and the memory structure; 
 wherein the ground and string selection structures comprise MOSFETs using the substrate as channel regions therein, and 
 wherein the memory structure comprises MOSFETs, which are sequentially stacked over the substrate and use the semiconductor pattern as channel regions therein. 
 
     
     
       8. The device of  claim 7 , further comprising information storing element between the semiconductor pattern and the memory structure. 
     
     
       9. The device of  claim 8 , wherein the information storing element comprises a charge storing layer. 
     
     
       10. The device of  claim 7 , further comprising a ground selection line and a string selection line parallel with the word lines,
 wherein the ground and string selection lines are used as gate electrodes of the MOSFETs for the ground and string selection structures, respectively, and 
 wherein the word lines stacked sequentially are used as gate electrodes of the MOSFETs for the memory structure. 
 
     
     
       11. The device of  claim 10 , wherein the ground selection structure comprises first and second doped regions formed in the substrate at both sides of the ground selection line, the first and second doped regions being coupled to the semiconductor pattern and a common source line parallel to the ground selection line, respectively, and
 wherein the string selection structure comprises third and fourth doped regions formed in the substrate at both sides of the string selection line, the third and fourth doped regions being coupled to the semiconductor pattern and a bit line crossing the string selection line, respectively. 
 
     
     
       12. A non-volatile memory device, comprising:
 a NAND-type string of non-volatile memory cells including:
 at least a first vertically-stacked array of charge trap memory cells on a semiconductor substrate, said first vertically-stacked array of charge trap memory cells comprising a semiconductor layer that covers first and second opposing sidewalls thereof, said semiconductor layer containing channel regions of the first vertically-stacked array of charge trap memory cells therein; 
 a string select transistor on a first side of the first vertically-stacked array of charge trap memory cells, said string select transistor having a first source/drain terminal electrically connected to the semiconductor layer; and 
 a ground select transistor on a second side of the first vertically stacked array of charge trap memory cells, said string select and ground select transistors having respective channel regions in the semiconductor substrate. 
 
 
     
     
       13. The device of  claim 12 , wherein the semiconductor layer is electrically connected to a first source/drain terminal of the ground select transistor. 
     
     
       14. The device of  claim 12 , wherein the semiconductor substrate comprises an electrically insulating layer therein; and wherein said first vertically-stacked array of charge trap memory cells is disposed on the electrically insulating layer. 
     
     
       15. The device of  claim 14 , wherein said NAND-type string of non-volatile memory cells comprises a second vertically-stacked array of charge trap memory cells on the electrically insulating layer; and wherein the semiconductor layer covers first and second opposing sidewalls of the second vertically-stacked array of charge trap memory cells. 
     
     
       16. The device of  claim 13 , further comprising:
 a bit line electrically coupled to a second source/drain terminal of the string select transistor; and 
 a ground select line electrically coupled to a second source/drain terminal of the ground select transistor. 
 
     
     
       17. The device of  claim 12 , wherein all of the cells in the first vertically-stacked array of charge trap memory cells are configured to store nonvolatile data when programmed.