Data driving apparatus and display device comprising the same

Abstract

A data driving apparatus includes a horizontal synchronization start signal generation circuit and data driving circuit. The horizontal synchronization start signal generation circuit generates a horizontal synchronization start signal using image data signals. The data driving circuit samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal. The horizontal synchronization start signal generation circuit is disabled in response to the load signal.

What is claimed is: 
     
       1. A data driving apparatus comprising:
 a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal using image data signals; and 
 a data driving circuit that samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal, 
 wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal, 
 wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when at least two last bits of the image data signals are a same logic level, and 
 wherein the horizontal synchronization start signal is derived from the at least two last bits. 
 
     
     
       2. The data driving apparatus of  claim 1 , wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the data driving circuit provides the respective data signals in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. 
     
     
       3. The data driving apparatus of  claim 2 , wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when the k bits of the image data signals included in the horizontal synchronization start signal generation period are all at high levels. 
     
     
       4. The data driving apparatus of  claim 2 , wherein k is less than j. 
     
     
       5. The data driving apparatus of  claim 1 , wherein the horizontal synchronization start signal generation circuit comprises:
 a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals; and 
 an operation unit that performs an operation on output signals supplied from at least two flip-flops among the plurality of flip-flops. 
 
     
     
       6. The data driving apparatus of  claim 5 , wherein the load signal is input to a reset terminal of each of the plurality of flip-flops. 
     
     
       7. The data driving apparatus of  claim 6 , wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops. 
     
     
       8. The data driving apparatus of  claim 5 , wherein the operation unit performs AND operations on output signals supplied from at least two flip-flops among the plurality of flip-flops. 
     
     
       9. The data driving apparatus of  claim 1 , wherein the data driving circuit comprises:
 a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to the load signal; 
 a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and 
 a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals. 
 
     
     
       10. A data driving apparatus comprising:
 a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal when at least two last bits of image data signals are a same logic level, the horizontal synchronization start signal being derived from the at least two last bits, the horizontal synchronization start signal generation circuit including a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals, and an operation unit that performs a logical operation on output signals supplied from at least two flip-flops among the plurality of flip-flops to generate the horizontal synchronization start signal, wherein the logical operation indicates whether all of the output signals supplied from the at least two flip-flops to the operation unit have a same logic level; 
 a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to a load signal; 
 a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and 
 a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals, 
 wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal. 
 
     
     
       11. The data driving apparatus of  claim 10 , wherein the load signal is input to a reset terminal of each of the plurality of flip-flops of the horizontal synchronization start signal generation circuit. 
     
     
       12. The data driving apparatus of  claim 11 , wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops of the horizontal synchronization start signal generation circuit. 
     
     
       13. The data driving apparatus of  claim 10 , wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the respective data signals are provided in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. 
     
     
       14. A display device comprising:
 a display panel that includes a plurality of unit pixels at intersections of a plurality of gate lines and a plurality of data lines; 
 a timing controller that provides data control signals and image data signals; and 
 a data driver that applies data signals to the plurality of data lines in response to the data control signals and the image data signal, the data driver comprising:
 a horizontal synchronization start signal generation circuit that generates a horizontal synchronization start signal from an output of a logical operation performed on image data signals, wherein the horizontal synchronization start signal is generated when the logical operation indicates that at least two last bits of the image data signals are a same logic level, the horizontal synchronization start signal being an output of the logical operation; and 
 a data driving circuit that samples the image data signals in response to the horizontal synchronization start signal and supplies a plurality of data signals using the sampled image data signals in response to a load signal, 
 wherein the horizontal synchronization start signal generation circuit is disabled in response to the load signal. 
 
 
     
     
       15. The display device of  claim 14 , wherein the horizontal synchronization start signal generation circuit comprises:
 a plurality of flip-flops that are connected to one another in a cascade manner, supplied with and sequentially outputting the image data signals; and 
 an operation unit that performs the logical operation on output signals supplied from at least two flip-flops among the plurality of flip-flops, wherein the logical operation indicates whether all of the output signals supplied from the least two flip-flops to the operation unit are a same logic level; 
 wherein the data driving circuit comprises:
 a shift register that samples the image data signals in response to the horizontal synchronization start signal and a data sampling clock signal, and outputs the sampled image data signals in response to a load signal; 
 a digital-to-analog converter that receives the sampled image data signals from the shift register and outputs a plurality of analog data signals corresponding to the sampled data signals; and 
 a buffer that is supplied with the plurality of analog data signals, selects polarities of the analog data signals and provides the selected polarities to the data signals. 
 
 
     
     
       16. The display device of  claim 15 , wherein the load signal is input to a reset terminal of each of the plurality of flip-flops. 
     
     
       17. The display device of  claim 16 , wherein the load signal or a delayed signal of the load signal is input to a reset terminal of each of the plurality of flip-flops. 
     
     
       18. The display device of  claim 15 , wherein the operation unit performs AND operations on output signals supplied from at least two flip-flops among the plurality of flip-flops. 
     
     
       19. The display device of  claim 14 , wherein the image data signals have a horizontal synchronization start signal generation period and an effective image data period, the data driving circuit provides the respective data signals in the effective image data period using j bits of the image data signals, and the horizontal synchronization start signal generation circuit provides the horizontal synchronization start signal using k bits of the image data signals included in the horizontal synchronization start signal generation period, wherein j and k are natural numbers. 
     
     
       20. The display device of  claim 19 , wherein the horizontal synchronization start signal generation circuit generates the horizontal synchronization start signal when the k bits of the image data signals included in the horizontal synchronization start signal generation period are all at high levels.