High value resistors in gallium arsenide

Abstract

A high value resistor of the present invention has an active layer deposited over a semi-insulating substrate. Channel etch regions are defined within the active layer. Gate metal is deposited over each channel etch region. Ohmic contact material is deposited at opposing ends of the active layer to define connection regions. A second metal is deposited over the connection regions to form input/output pads. This resistor pattern presents significant increase in resistance in a given area without any additional processing or process steps.

I claim: 
     
       1. A device comprising:
 a resistor including: 
 a semi-insulating substrate; 
 an active layer, positioned over the semi-insulating substrate, including an epitaxial layer designed for enhancement mode operation; 
 a first channel region positioned over the active layer; 
 a first gate metal covering a portion of the first channel region; 
 ohmic contact material positioned at opposing ends of the active layer; 
 a second gate metal covering a portion of the first channel region; and 
 metal positioned over the opposing ends of the active layer to form input/output pads. 
 
     
     
       2. A device comprising:
 a resistor including:
 a semi-insulating substrate; 
 an active layer, positioned over the semi-insulating substrate, including an epitaxial layer designed for enhancement mode operation; 
 a first channel region positioned over the active layer; 
 a first gate metal covering a portion of the first channel region; 
 ohmic contact material positioned at opposing ends of the active layer; 
 a second channel region covering a portion of the active layer; 
 a second gate metal covering a portion of the second channel region; and 
 metal positioned over the opposing ends of the active layer to form input/output pads. 
 
 
     
     
       3. A device comprising:
 a resistor including:
 a semi-insulating substrate; 
 an active layer, positioned over the semi-insulating substrate, including an epitaxial layer designed for enhancement mode operation; 
 a first channel region having a serpentine shape, positioned over the active layer; 
 a first gate metal covering a portion of the first channel region; 
 ohmic contact material positioned at opposing ends of the active layer; 
 a second gate metal covering a portion of the first channel region; and 
 metal positioned over the opposing ends of the active layer to form input/output pads.