Programmable logic based on a magnetic diode and applications of same

Abstract

In one aspect, the invention relates to programmable logic that utilizes one or more of magnetic diodes. By changing magnetic fields generated in the magnetic diodes due to input signals, the programmable logic can be changed from one logic gate to another logic gate. The unique feature leads to field reprogrammable logic devices in which simple instructions can be used to construct a whole new set of logic gates.

What is claimed is: 
     
       1. A programmable logic cell, comprising:
 a magnetic diode having a non-magnetic semiconductor layer and a magnetic semiconductor layer disposed on the non-magnetic semiconductor layer, wherein the magnetic diode is configured such that under a forward bias, when a magnetic field applied to the magnetic diode is less than a threshold value, the magnetic diode is in a conductive state in which electric current flows through the magnetic diode, and when the magnetic field applied to the magnetic diode is greater than the threshold value, the magnetic diode is in a resistive state in which the electric current flowing through the magnetic diode is substantially reduced; 
 a first input wire for receiving a first input current, and a second input wire for receiving a second input current, wherein the first and second input wires are oriented along a first direction parallel to the magnetic semiconductor layer of the magnetic diode and positioned spaced-apart along a second direction perpendicular to the first direction over the magnetic semiconductor layer of the magnetic diode, such that when either of the first input current and the second input current flows through a respective input wire of the first input wire and the second input wire and no current flows through the other input wire, a magnetic field B generated in the magnetic diode is less than the threshold value, and when both the first input current and the second input current flow through the first input wire and the second input wire, respectively, along the same direction, the magnetic field generated in the magnetic diode is greater than the threshold value; and 
 an output wire oriented along a third direction perpendicular to the first and second directions and positioned under the non-magnetic semiconductor layer of the magnetic diode for outputting a logic “0” or “1” responsive to the first input current and the second input current. 
 
     
     
       2. The programmable logic cell of  claim 1 , being a logic NAND gate. 
     
     
       3. The programmable logic cell of  claim 1 , further comprising an operation control wire paralelly positioned over the first input wire for receiving an operation control current, so as to implement a logic OR gate, a logic AND gate, or a logic NOR gate. 
     
     
       4. The programmable logic cell of  claim 3 , wherein the operation control current is configured to flow through the operation control wire in a direction opposite to the current flow in the first and second input wire in such a way that magnetic field due to the operation control current nullifies the magnetic field generated when there is the current flowing in the first and second input wires, thereby implementing the logic OR gate. 
     
     
       5. The programmable logic cell of  claim 4 , wherein the operation control current is increased by the first input current, thereby implementing the logic AND gate. 
     
     
       6. The programmable logic cell of  claim 3 , wherein the operation control current is configured to flow through the operation control wire in the same direction as the current flow in the first and second input wire in such a way that magnetic field due to the operation control current adds to the magnetic field generated when there is the current flowing in either of the first and second input wires resulting it greater than the threshold value, thereby implementing the logic NOR gate. 
     
     
       7. The programmable logic cell of  claim 1 , wherein the non-magnetic semiconductor layer comprises an n-type doped III-V compound containing an element of Group III and an element of Group V. 
     
     
       8. The programmable logic cell of  claim 7 , wherein the non-magnetic semiconductor layer comprises n-type doped InAs. 
     
     
       9. The programmable logic cell of  claim 1 , wherein the magnetic semiconductor layer comprises a p-type doped III-Mn-V compound containing an element of Group III, Manganese (Mn) and an element of Group V. 
     
     
       10. The programmable logic cell of  claim 9 , wherein the magnetic semiconductor layer comprises p-type doped InMnAs. 
     
     
       11. A programmable logic apparatus, comprising at least one reprogrammable logic cell of  claim 1 . 
     
     
       12. A programmable logic cell, comprising:
 a first magnetic diode having a cathode connected to a first input port for receiving a first input signal and an anode; 
 a second magnetic diode having a cathode connected to a second input port for receiving a second input signal and an anode connected to the anode of the first magnetic diode; 
 a transistor having a base connected to the anode of the second magnetic diode and a collector connected to an output port for outputting a logic “0” or “1” responsive to the first and second input signals, and an emitter connected to ground; 
 a first resistor having a first terminal connected to a voltage source having a positive voltage and a second terminal connected to the anode of the first magnetic diode; and 
 a second resistor having a first terminal connected to the voltage source and a second terminal connected to the collector of the transistor, 
 wherein each magnetic diode is configured such that under a forward bias, when a magnetic field applied to the magnetic diode is less than a threshold value, the magnetic diode is in a conductive state in which electric current flows through the magnetic diode, and when the magnetic field applied to the magnetic diode is greater than the threshold value, the magnetic diode is in a resistive state in which the electric current flowing through the magnetic diode is substantially reduced; and 
 wherein each of the first input signal and the second input signal is a low voltage for which a corresponding one of the first and second magnetic diodes is forward-biased or a high voltage for which the corresponding one of the first and second magnetic diodes is reverse-biased. 
 
     
     
       13. The programmable logic cell of  claim 12 , being a logic NAND gate. 
     
     
       14. The programmable logic cell of  claim 12 , being a logic AND gate when a magnetic field is applied to the first and second magnetic diodes. 
     
     
       15. A programmable logic apparatus, comprising at least one reprogrammable logic cell of  claim 12 . 
     
     
       16. A programmable logic cell, comprising:
 a first diode having a cathode connected to a first input port for receiving a first input signal and an anode; 
 a second diode having a cathode connected to a second input port for receiving a second input signal and an anode connected to the anode of the first diode; 
 a transistor having a base electrically coupled to the anode of the second diode and a collector connected to an output port for outputting a logic “0” or “1” responsive to the first and second input signals, and an emitter connected to ground; 
 a magnetic diode having a cathode and an anode connected to a voltage source having a positive voltage, wherein the magnetic diode is configured such that under a forward bias, when a magnetic field applied to the magnetic diode is less than a threshold value, the magnetic diode is in a conductive state in which electric current flows through the magnetic diode, and when the magnetic field applied to the magnetic diode is greater than the threshold value, the magnetic diode is in a resistive state in which the electric current flowing through the magnetic diode is substantially reduced; 
 a first resistor having a first terminal and a second terminal connected to the anode of the first diode; and 
 a second resistor having a first terminal and a second terminal connected to the collector of the transistor, 
 wherein the first terminal of one of the first and second resistors is connected to the cathode of the magnetic diode and the first terminal of the other of the first and second resistors is connected to the voltage source; and 
 wherein each of the first input signal and the second input signal is a low voltage for which a corresponding one of the first and second diodes is forward-biased or a high voltage for which the corresponding one of the first and second diodes is reverse-biased. 
 
     
     
       17. The programmable logic cell of  claim 16 , being a logic NAND gate, wherein the output port outputs the logic “1”, when both the first and second input ports receive the low voltage, or when either of the first and second input ports receives the high voltage and the other receives the low voltage, and wherein the output port outputs the logic “0”, when both the first and second input ports receive the high voltage. 
     
     
       18. The programmable logic cell of  claim 16 , being a logic AND gate when a magnetic field is applied to the magnetic diode. 
     
     
       19. The programmable logic cell of  claim 16 , further comprising a third diode having a cathode connected to the base of the transistor and an anode connected to the anode of the second diode. 
     
     
       20. The programmable logic cell of  claim 16 , wherein at least one of the first, second and third diodes is a magnetic diode. 
     
     
       21. A programmable logic apparatus, comprising at least one reprogrammable logic cell of  claim 16 . 
     
     
       22. A programmable logic cell, comprising:
 a multi-emitter transistor having a base, three emitters connected respectively to a first input port for receiving a first input signal, a second input port for receiving a second input signal and an operation control port for receiving a control signal, and a collector, wherein the multi-emitter transistor comprises a bipolar magnetic junction transistor having a magnetic diode configured such that under a forward bias, when a magnetic field applied to the magnetic diode responsive to the control signal is less than a threshold value, the magnetic diode is in a conductive state in which electric current flows through the magnetic diode, and when the magnetic field applied to the magnetic diode is greater than the threshold value, the magnetic diode is in a resistive state in which the electric current flowing through the magnetic diode is substantially reduced; 
 a first resistor having a first terminal connected to a voltage source having a positive voltage and a second terminal connected to the base of the multi-emitter transistor; 
 a second resistor having a first terminal connected to the voltage source and a second terminal; and 
 a first transistor having a base connected to the collector of the multi-emitter transistor, a collector connected to the second terminal of the second resistor and electrically coupled to an output port for outputting logic “0” or “1” responsive to the first and second input signals and the control signal, and an emitter electrically coupled to ground. 
 
     
     
       23. The programmable logic cell of  claim 22 , wherein the magnetic diode is formed of a magnetic semiconductor layer and a non-magnetic semiconductor layer. 
     
     
       24. The programmable logic cell of  claim 23 , wherein the non-magnetic semiconductor layer comprises an n-type doped III-V compound containing an element of Group III and an element of Group V. 
     
     
       25. The programmable logic cell of  claim 24 , wherein the non-magnetic semiconductor layer comprises n-type doped InAs. 
     
     
       26. The programmable logic cell of  claim 23 , wherein the magnetic semiconductor layer comprises a p-type doped III-Mn-V compound containing an element of Group III, Manganese (Mn) and an element of Group V. 
     
     
       27. The programmable logic cell of  claim 26 , wherein the magnetic semiconductor layer comprises p-type doped InMnAs. 
     
     
       28. The programmable logic cell of  claim 22 , further comprising:
 a third resistor having a first terminal connected to the voltage source and a second terminal; 
 a fourth resistor having a first terminal connected to the emitter of the first transistor and a second terminal connected to the ground; 
 a second transistor having a base connected to the collector of the first transistor, a collector connected to the second terminal of the third resistor, and an emitter; 
 a third transistor having a base connected to the emitter of the first transistor, a collector connected to the output port, and an emitter connected to the ground; and 
 a diode having an anode connected to the emitter of the second transistor and a cathode connected to the collector of the third transistor. 
 
     
     
       29. The programmable logic cell of  claim 22 , being a logic NAND gate. 
     
     
       30. The programmable logic cell of  claim 22 , being a logic AND gate when a magnetic field is applied to the magnetic diode. 
     
     
       31. A programmable logic apparatus, comprising at least one reprogrammable logic cell of  claim 22 .